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features description tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 low power stereo audio codec for portable audio/telephony stereo audio dac the tlv320aic31 is a low-power stereo-audio codec with a stereo headphone amplifier, as well as ? 100 db a signal-to-noise ratio multiple inputs and outputs, programmable in ? 16/20/24/32-bit data single-ended or fully-differential configurations. ? supports rates from 8 khz to 96 khz extensive register-based power control is included, ? 3d/bass/treble/eq/de-emphasis effects enabling stereo 48-khz dac playback as low as 14 mw from a 3.3-v analog supply, making it ideal for stereo audio adc portable, battery-powered audio and telephony ? 92 db a signal-to-noise ratio applications. ? supports rates from 8 khz to 96 khz the record path of the tlv320aic31 contains six audio input pins integrated microphone bias, digitally-controlled ? two stereo differential/single-ended inputs stereo-microphone pre-amp, and automatic gain control (agc), with mix/mux capability among the six audio output drivers multiple analog inputs. the playback path includes ? stereo 8- w , 500 mw/channel speaker drive mix/mux capability from the stereo dac and selected capability inputs, through programmable volume controls, to the various outputs. ? stereo fully-differential or single-ended headphone drivers the tlv320aic31 contains four high-power output ? fully differential stereo line outputs drivers as well as two fully differential output drivers. the high-power output drivers are capable of driving low power: 14-mw stereo, 48-khz playback a variety of load configurations, including up to four with 3.3-v analog supply channels of single-ended 16- w headphones using programmable input/output analog gains ac-coupling capacitors, or stereo 16- w headphones automatic gain control (agc) for record in a cap-less output configuration. in addition, pairs of drivers can be used to drive 8- w speakers in a programmable microphone bias level btl configuration at 500 mw per channel. programmable pll for flexible clock the stereo audio dac supports sampling rates from generation 8 khz to 96 khz and includes programmable digital i 2 c control bus filtering in the dac path for 3d, bass, treble, audio serial data bus supports i 2 s, midrange effects, speaker equalization, and left/right-justified, dsp, and tdm modes de-emphasis for 32 khz, 44.1 khz, and 48 khz rates. the stereo-audio adc supports sampling rates from extensive modular power control 8 khz to 96 khz and is preceded by programmable power supplies: gain amplifiers providing up to +59.5 db analog gain ? analog: 2.7 v ? 3.6 v for low-level microphone inputs. ? digital core: 1.525 v ? 1.95 v the serial control bus supports the i 2 c protocol, ? digital i/o: 1.1 v ? 3.6 v while the serial-audio data bus is programmable for i 2 s, left/right justified, dsp, or tdm modes. a highly available packages: 5 5 mm, 32-pin qfn programmable pll is included for flexible clock generation and support for all standard audio rates from a wide range of available mclks, varying from 512 khz to 50 mhz, with special attention paid to the most popular cases of 12 mhz, 13 mhz, 16 mhz, 19.2 mhz, and 19.68 mhz system clocks. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2006, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.

simplified block diagram tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 the tlv320aic31 operates from an analog supply of 2.7 v ? 3.6 v, a digital core supply of 1.525 v ? 1.95 v, and a digital i/o supply of 1.1 v ? 3.6 v. the device is available in a 5 5 mm, 32-lead qfn package. figure 1. simplified codec block diagram package/ordering information operating package transport product package temperature ordering number designator media, quantity range tlv320aic31 qfn-32 rhb ?40 c to 85 c tlv320aic31irhbt tape and reel, 250 tlv320aic31irhbr tape and reel, 3000 2 submit documentation feedback www .ti.com line_out_l+line_out_l? line_out_r+ line_out_r? hpr+ hpr?/hprcom/spkfc hpl?/hplcom hpl+ mixing, muxing,volume controls mixing, muxing pga 0/+59.5db 0.5db steps pga 0/+59.5db 0.5db steps adc adc audio serial bus dac dac din dout bclk wclk i2c serial control bus audio clock generation mclk bias/ reference micbias v oltage supplies avdd_dac avss_dac drvdd drvss dvss v olume ctl & effects v olume ctl & effects drvdd scl sda avss_adc resetb in1l+in1l? in2l in2r in1r+ in1r? dvdd iovdd
device information pin assignments tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 terminal functions terminal description name qfn no. i/o mclk 1 i master clock input bclk 2 i/o audio serial data bus bit clock input/output wclk 3 i/o audio serial data bus word clock input/output din 4 i audio serial data bus data input dout 5 o audio serial data bus data output dvss 6 i/o digital core / i/o ground supply, 0 v iovdd 7 i/o digital i/o voltage supply, 1.1 v ? 3.6 v scl 8 i/o i2c serial clock input sda 9 i/o i2c serial data input/output in1lp 10 i left input 1 (se) or left input + (diff) in1lm 11 i left input - (diff only) in1rp 12 i right input 1 (se) or right input + (diff) in1rm 13 i right input - (diff only) in2l 14 i left input 2 (se) micbias 15 o microphone bias voltage output in2r 16 i right input 2 (se) avss1 17 i analog adc ground supply, 0 v drvdd 18 o analog adc and output driver voltage supply, 2.7 v ? 3.6 v hplout 19 o high power output driver (left +) hplcom 20 o high power output driver (left - or multi-functional) drvss 21 o analog output driver ground supply, 0 v hprcom 22 o high power output driver (right - or multi-functional) hprout 23 o high power output driver (right +) drvdd 24 o analog output driver voltage supply, 2.7 v ? 3.6 v avdd 25 i analog dac voltage supply, 2.7 v ? 3.6 v avss2 26 i analog dac ground supply, 0 v left_lop 27 o left line output (+) left_lom 28 o left line output (-) right_lop 29 o right lineo output (+) 3 submit documentation feedback www .ti.com 1 (bottom view) 8 9 16 17 24 25 32 this is a test
absolute maximum ratings dissipation ratings (1) recommended operating conditions tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 device information (continued) terminal functions (continued) terminal description name qfn no. i/o right_lom 30 o right line output (-) reset 31 reset dvdd 32 i digital core voltage supply, 1.525 v ? 1.95 v over operating free-air temperature range (unless otherwise noted) (1) value unit avdd to avss1/2, drvdd1/2 to drvss ?0.3 to 3.9 v avdda1 to drvss ?0.3 to 3.9 v iovdd to dvss ?0.3 to 3.9 v dvdd to dvss ?0.3 to 2.5 v avdd to drvdd1/2 ?0.1 to 0.1 v digital input voltage to dvss ?0.3 v to iovdd+0.3 v analog input voltage to avss ?0.3 v to avdd+0.3 v operating temperature range -40 to +85 c storage temperature range -65 to +105 c t j junction temperature 105 c max power dissipation (t j max ? t a ) / q ja qfn package q ja thermal impedance tbd soldering vapor phase (60 sec.) tbd lead temperature infrared (15 sec.) tbd (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. t a = 25 c t a = 75 c t a = 85 c derating factor power rating power rating power rating 1.82 w 22.7 mw/ c 681 mw 454 mw (1) this data was taken using 2 oz. trace and copper pad that is soldered directly to a jedec standard 4-layer 3 in 3 in pcb. over operating free-air temperature range (unless otherwise noted) min nom max unit avdd, analog supply voltage 2.7 3.3 3.6 v drvdd1/2 (1) dvdd (1) digital core supply voltage 1.525 1.8 1.95 v iovdd (1) digital i/o supply voltage 1.1 1.8 3.6 v v i analog full-scale 0 db input voltage (drvdd1 = 3.3 v) 0.707 v rms stereo line-output load resistance 10 k w stereo headphone-output load resistance 16 w digital output load capacitance 10 pf t a operating free-air temperature ?40 85 c (1) analog voltage values are with respect to avss1, avss2, drvss; digital voltage values are with respect to dvss. 4 submit documentation feedback www .ti.com
electrical characteristics tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 at 25 c, avdd, drvdd, iovdd = 3.3 v, dvdd = 1.8 v, fs = 48-khz, 16-bit audio data (unless otherwise noted) parameter test conditions min typ max unit audio adc input signal level (0-db) single-ended input 0.707 v rms signal-to-noise ratio, fs = 48 khz, 0 db pga gain, in1 inputs selected and 80 92 db a-weighted (1) (2) ac-shorted together fs = 48 khz, 1-khz ?60 db full-scale input applied at dynamic range, a-weighted (1) (2) 92 db in1 inputs, 0-db pga gain ?90 -75 db fs = 48 khz, 1-khz ?2db full-scale input applied at thd total harmonic distortion in1 inputs, 0-db pga gain 0.003% 0.018% 1 khz, 100 mvpp on avdd, drvdd, single-ended 46 input power supply rejection ratio db 1 khz, 100 mvpp on avdd, drvdd, differential input 68 adc channel separation 1 khz, ?1 db in2l to in2r ?87 db adc gain error 1 khz input, 0 db pga gain 0.7 db adc programmable gain 1-khz input tone, r source < 50 w 59.5 db amplifier maximum gain adc programmable gain 0.5 db amplifier step size in1 inputs, routed to single adc 20 input mix attenuation = 0 db in2 inputs, input mix attenuation = 0 db 20 input resistance k w in1 inputs, 80 input mix attenuation = ?12 db in2 inputs, 80 input mix attenuation = ?12 db input capacitance in1 inputs 10 pf input level control minimum 0 db attenuation setting input level control maximum 12 db attenuation setting input level control attenuation 1.5 db step size adc digital decimation filter, fs = 48 khz filter gain from 0 to 0.39 fs 0.1 db filter gain at 0.4125 fs ?0.25 db filter gain at 0.45 fs ?3 db filter gain at 0.5 fs ?17.5 db filter gain from 0.55 fs to 64 fs ?75 db filter group delay 17/fs sec microphone bias 2.0 2.25 2.5 2.75 bias voltage programmable settings, load = 750 w v avdd- 0.2 current sourcing 2.5 v setting 4 ma (1) ratio of output level with 1-khz full-scale sine wave input, to the output level with the inputs short circuited, measured a-weighted over a 20-hz to 20-khz bandwidth using an audio analyzer. (2) all performance measurements done with 20-khz low-pass filter and, where noted, a-weighted filter. failure to use such a filter may result in higher thd+n and lower snr and dynamic range readings than shown in the electrical characteristics. the low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. 5 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 electrical characteristics (continued) at 25 c, avdd, drvdd, iovdd = 3.3 v, dvdd = 1.8 v, fs = 48-khz, 16-bit audio data (unless otherwise noted) parameter test conditions min typ max unit audio dac differential line output, load = 10 k w , 50 pf 1.414 v rms full-scale differential output 0-db gain to line outputs. dac output common-mode voltage setting = 1.35 v, output level control gain = 0-db 4.0 v pp signal-to-noise ratio, fs = 48 khz, 0-db gain to line outputs, zero signal 90 100 db a-weighted (3) applied, referenced to full-scale input level fs = 48 khz, 0-db gain to line outputs, dynamic range, a-weighted 100 db 1 khz ?60 db signal applied total harmonic distortion fs = 48 khz, 1 khz 0 db input signal applied ?93 ?75 db power supply rejection ratio 234 hz, 100 mvpp on avdd, drvdd1/2 81 db dac channel separation (left to 1-khz, 0-db ?100 db right) dac interchannel gain mismatch 1 khz input, 0db gain 0.1 db dac gain error 1 khz input, 0db gain ?0.26 db dac digital interpolation fs = 48-khz filter passband high-pass filter disabled 0.45 fs hz passband ripple high-pass filter disabled 0.06 db transition band 0.45 fs 0.55 fs hz stopband 0.55 fs 7.5 fs hz stopband attenuation 65 db group delay 21/fs sec stereo headphone driver ac-coupled output configuration (4) 0-db gain to high power outputs. output 0-db full-scale output voltage 0.707 v rms common-mode voltage setting = 1.35 v first option 1.35 programmable output common second option 1.50 mode voltage (applicable to line v third option 1.65 outputs also) fourth option 1.8 maximum programmable output 9 db level control gain programmable output level 1 db control gain step size r l = 32 w 15 p o maximum output power mw r l = 16 w 30 signal-to-noise ratio, 94 db a-weighted (5) ?77 1-khz output, p o = 10 mw, r l = 32 w 0.014% ?80 1-khz output, p o = 20 mw, r l = 32 w 0.01% total harmonic distortion db ?77 1-khz output, p o = 20 mw, r l = 16 w 0.014% ?76 1-khz output, p o = 30 mw, r l = 16 w 0.016% (3) unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 v, 0-db output level control gain, 16- w single-ended load. (4) unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 v, 0-db output level control gain, 16- w single-ended load. (5) ratio of output level with a 1-khz full-scale input, to the output level playing an all-zero signal, measured a-weighted over a 20-hz to 20-khz bandwidth. 6 submit documentation feedback www .ti.com
audio data serial interface timing diagram tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 electrical characteristics (continued) at 25 c, avdd, drvdd, iovdd = 3.3 v, dvdd = 1.8 v, fs = 48-khz, 16-bit audio data (unless otherwise noted) parameter test conditions min typ max unit channel separation 1 khz, 0 db input 96 db power supply rejection ratio 217 hz, 100 mvpp on avdd, drvdd1/2 48 db mute attenuation 1-khz output 107 db digital i/o 0.3 v il input low level i il = +5- m a ?0.3 v iovdd 0.7 v ih input high level (6) i ih = +5- m a v iovdd 0.1 v ol output low level i ih = 2 ttl loads v iovdd 0.8 v oh output high level i oh = 2 ttl loads v iovdd supply current fs = 48-khz avdd+drvdd 3.0 fs = 48-khz, pll off, headphone stereo line playback ma drivers off, dac direct mode dvdd 2.0 avdd+drvdd 2.3 mono record fs = 48-khz, pll and agc off ma dvdd 1.1 avdd+drvdd 4.3 stereo record fs = 48-khz, pll and agc off ma dvdd 1.3 avdd+drvdd 1.3 additional power consumed when pll ma pll is powered dvdd 0.9 avdd+drvdd analog bypass to single-ended 1.5 headphone amplifier headphones, dac and pll off, no ma dvdd 0 signal applied avdd+drvdd all supply voltages applied, all 0.1 power down blocks programmed in lowest m a dvdd 0.5 power state (6) when iovdd < 1.6v, minimum vih is 1.1v. figure 2. i2s/ljf/rjf timing in master mode 7 submit documentation feedback www .ti.com wclk sdout bclk sdin td (ws) td (do-ws) td (do-bclk) ts (di) th (di)
timing characteristics (1) timing characteristics (1) tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 all specifications typical at 25 c, dvdd = 1.8 v iovdd = 1.1 v iovdd = 3.3 v parameter unit min max min max t d (ws) adws/wclk delay time 50 15 ns t d (do-ws) adws/wclk to dout delay time 50 20 ns t d (do-bclk) bclk to dout delay time 50 15 ns t s (di) din setup time 10 6 ns t h (di) din hold time 10 6 ns t r rise time 30 10 ns t f fall time 30 10 ns (1) all timing specifications are measured at characterization but not tested at final test. figure 3. dsp timing in master mode all specifications typical at 25 c, dvdd = 1.8 v iovdd = 1.1 v iovdd = 3.3 v parameter unit min max min max t d (ws) adws/wclk delay time 50 15 ns t d (do-bclk) bclk to dout delay time 50 15 ns t s (di) din setup time 10 6 ns t h (di) din hold time 10 6 ns t r rise time 30 10 ns t f fall time 30 10 ns (1) all timing specifications are measured at characterization but not tested at final test. 8 submit documentation feedback www .ti.com wclk bclk sdout sdin t d(ws) t d(ws) t d(do-bclk) t s(di) t h(di)
timing characteristics (1) tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 figure 4. i2s/ljf/rjf timing in slave mode all specifications typical at 25 c, dvdd = 1.8 v iovdd = 1.1 v iovdd = 3.3 v parameter unit min max min max t h (bclk) bclk high period 70 35 ns t l (bclk) bclk low period 70 35 ns t s (ws) adws/wclk setup time 10 6 ns t h (ws) adws/wclk hold time 10 6 ns t d bclk to dout delay time 50 20 ns (do-bclk) t s (di) din setup time 10 6 ns t h (di) din hold time 10 6 ns t r rise time 8 4 ns t f fall time 8 4 ns (1) all timing specifications are measured at characterization but not tested at final test. figure 5. dsp timing in slave mode 9 submit documentation feedback www .ti.com t l(bclk) t p(bclk) t s(ws) t h(ws) t h(bclk) t d(do-ws) t d(do-bclk) t s(di) t h(di) wclk sdout bclk sdin wclk bclk sdout sdin t h(bclk) t h(ws) t l(bclk) t s(ws) t p(bclk) t h(ws) t d(do-bclk) t s(ws) t s(di) t h(di)
timing characteristics (1) typical characteristics tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 all specifications typical at 25 c, dvdd = 1.8 v iovdd = 1.1 v iovdd = 3.3 v parameter unit min max min max t h (bclk) bclk high period 70 35 ns t l (bclk) bclk low period 70 35 ns t s (ws) adws/wclk setup time 10 8 ns t h (ws) adws/wclk hold time 10 8 ns t d bclk to dout delay time 50 20 ns (do-bclk) t s (di) din setup time 10 6 ns t h (di) din hold time 10 6 ns t r rise time 8 4 ns t f fall time 8 4 ns (1) all timing specifications are measured at characterization but not tested at final test. figure 6. headphone power vs thd, 16 w load figure 7. headphone power vs thd, 32 w load 10 submit documentation feedback www .ti.com -90 -80 -70 -60 -50 -40 -30 -20 0.015 0.02 0.025 0.03 0.035 0.04 capless, vdd = 3.6 v capless, vdd = 2.7 v ac-coupled, vdd = 3.6 v ac-coupled, vdd = 2.7 v tota l harmo nic distortion - d b power - w 0.009 0.005 0.017 0.013 0.021 0.025 power - w -30 -20 -40-50 -60-70 -80 -90 thd - total harmonic distortion - db
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 typical characteristics (continued) figure 8. dac to line output fft plot figure 9. line input to adc fft plot 11 submit documentation feedback www .ti.com -140.00 -120.00 -100.00 -80.00 -60.00 -40.00 -20.00 0.00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 frequency - khz db -140 -120 -100 -80 -60 -40 -20 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 frequency - khz db
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 typical characteristics (continued) figure 10. speaker power vs thd, 8 w load figure 11. adc snr vs pga gain setting, ?65 dbfs input 12 submit documentation feedback www .ti.com vdd = 3.3 v vdd = 3.6 v vdd = 2.7 v -90.00 -80.00 -70.00 -60.00 -50.00 -40.00 -30.00 -20.00 -10.00 0.10 0.20 0.30 0.40 0.50 0.60 power - w thd 2 6 2 8 3 0 3 2 3 4 3 6 3 8 0 1 0 2 0 3 0 4 0 5 0 6 0 pga gain setting - db snr - db
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 typical characteristics (continued) figure 12. adc gain error vs pga gain setting figure 13. micbias output voltage vs avdd 13 submit documentation feedback www .ti.com 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 0 10 20 30 40 50 60 pga gain setting - db gain error - db left adc right adc micbias=2.0v micbias=2.5v micbias=avdd 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 avdd - v micbias - v
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 typical characteristics (continued) figure 14. micbias output voltage vs ambient temperature 14 submit documentation feedback www .ti.com micbias=2.0v micbias=2.5v micbias=avdd 1.8 2 2.2 2.4 2.6 2.8 3 3.2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temp - c micbias - v
typical circuit configuration tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 typical characteristics (continued) figure 15. typical connections for headphone and speaker drive 15 submit documentation feedback www .ti.com aic31 in2l in1lpin1rp in1lr in2r micbias avdd_dac avss_dac drvdd dvdd dvss iovdd drvdd drvss external audio power amplifiers tp a2012d2 (stereo class?d in wcsp) tp a2010d1 (mono class?d in wcsp) tp a2005d1 (mono class?d in bga, qfn, msop) a d 1.525?1.95v iovdd (1.1?3.3v) left_lop left_lom right_rop right_rom hprout hplcom hprcom a avdd (2.7v?3.6v) 1k hplout 8 8 sda scl r p r p iovdd /reset mclk bclk wclk dout din fm t uner/ line in/ mic dsp or media processor 1k a a in1rm analog baseband 0.1 m f 0.1 m f 0.47 m f 0.47 m f 0.47 m f 0.47 m f 0.47 m f 0.47 m f100 m f 100 m f 0.1 m f 1 m f 0.1 m f 1 m f 10 m f 0.1 m f 1 m f 1 m f 0.1 m f 1 m f 0.1 m f
overview hardware reset digital control serial interface i2c control interface tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 the tlv320aic31 is a highly flexible, low power, stereo audio codec with extensive feature integration, intended for applications in smartphones, pdas, and portable computing, communication, and entertainment applications. available in a 5 x 5 mm, 32-lead qfn, the product integrates a host of features to reduce cost, board space, and power consumption in space-constrained, battery-powered, portable applications. the tlv320aic31 consists of the following blocks: stereo audio multi-bit delta-sigma dac (8 khz ? 96 khz) stereo audio multi-bit delta-sigma adc (8 khz ? 96 khz) programmable digital audio effects processing (3-d, bass, treble, mid-range, eq, de-emphasis) four audio inputs four high-power audio output drivers (headphone/speaker drive capability) two fully differential line output drivers fully programmable pll headphone/headset jack detection with interrupt the tlv320aic31 requires a hardware reset after power-up for proper operation. after all power supplies are at their specified values, the reset pin must be driven low for at least 10 ns. if this reset sequence is not performed, the 'aic31 may not respond properly to register reads/writes. the register map of the tlv320aic31 actually consists of multiple pages of registers, with each page containing 128 registers. the register at address zero on each page is used as a page-control register, and writing to this register determines the active page for the device. all subsequent read/write operations will access the page that is active at the time, unless a register write is performed to change the active page. only two pages of registers are implemented in this product, with the active page defaulting to page 0 upon device reset. for example, at device reset, the active page defaults to page 0, and thus all register read/write operations for addresses 1 to 127 will access registers in page 0. if registers on page 1 must be accessed, the user must write the 8-bit sequence 0x01 to register 0, the page control register, to change the active page from page 0 to page 1. after this write, it is recommended the user also read back the page control register, to safely ensure the change in page control has occurred properly. future read/write operations to addresses 1 to 127 will now access registers in page 1. when page 0 registers must be accessed again, the user writes the 8-bit sequence 0x00 to register 0, the page control register, to change the active page back to page 0. after a recommended read of the page control register, all further read/write operations to addresses 1 to 127 will now access page 0 registers again. the tlv320aic31 supports the i2c control protocol, and will respond to the i2c address of 0011000. i2c is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. devices on the i2c bus only drive the bus lines low by connecting them to ground; they never drive the bus lines high. instead, the bus wires are pulled high by pull-up resistors, so the bus wires are high when no device is driving them low. this way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention. communication on the i2c bus always takes place between two devices, one acting as the master and the other acting as the slave. both masters and slaves can read and write, but slaves can only do so under the direction of the master. some i2c devices can act as masters or slaves, but the tlv320aic31 can only act as a slave device. an i2c bus consists of two lines, sda and scl. sda carries data; scl provides the clock. all data is transmitted across the i2c bus in groups of eight bits. to send a bit on the i2c bus, the sda line is driven to the appropriate level while scl is low (a low on sda indicates the bit is zero; a high indicates the bit is one). once the sda line has settled, the scl line is brought high, then low. this pulse on scl clocks the sda bit into the receiver's shift register. 16 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 overview (continued) the i2c bus is bidirectional: the sda line is used both for transmitting and receiving data. when a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. under most circumstances the master drives the clock line. most of the time the bus is idle, no communication is taking place, and both lines are high. when communication is taking place, the bus is active. only master devices can start a communication. they do this by causing a start condition on the bus. normally, the data line is only allowed to change state while the clock line is low. if the data line changes state while the clock line is high, it is either a start condition or its counterpart, a stop condition. a start condition is when the clock line is high and the data line goes from high to low. a stop condition is when the clock line is high and the data line goes from low to high. after the master issues a start condition, it sends a byte that indicates which slave device it wants to communicate with. this byte is called the address byte. each device on an i2c bus has a unique 7-bit address to which it responds. (slaves can also have 10-bit addresses; see the i2c specification for details.) the master sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to the slave device. every byte transmitted on the i2c bus, whether it is address or data, is acknowledged with an acknowledge bit. when a master has finished sending a byte (eight data bits) to a slave, it stops driving sda and waits for the slave to acknowledge the byte. the slave acknowledges the byte by pulling sda low. the master then sends a clock pulse to clock the acknowledge bit. similarly, when a master has finished reading a byte, it pulls sda low to acknowledge this to the slave. it then sends a clock pulse to clock the bit. a not-acknowledge is performed by simply leaving sda high during an acknowledge cycle. if a device is not present on the bus, and the master attempts to address it, it will receive a not?acknowledge because no device is present at that address to pull the line low. when a master has finished communicating with a slave, it may issue a stop condition. when a stop condition is issued, the bus becomes idle again. a master may also issue another start condition. when a start condition is issued while the bus is active, it is called a repeated start condition. the tlv320aic31 also responds to and acknowledges a general call, which consists of the master issuing a command with a slave address byte of 00h. figure 16. i2c write figure 17. i2c read in the case of an i2c register write, if the master does not issue a stop condition, then the device enters auto-increment mode. so in the next eight clocks, the data on sda is treated as data for the next incremental register. 17 submit documentation feedback www .ti.com da(6) da(0) ra(7) ra(0) d(7) d(0) start (m) 7-bit device address (m) write (m) slave ack (s) 8-bit register address (m) slave ack (s) 8-bit register data (m) stop (m) slave ack (s) sda scl (m) => sda controlled by master (s) => sda controlled by slave da(6) da(0) ra(7) ra(0) start (m) 7-bit device address (m) write (m) slave ack (s) 8-bit register address (m) slave ack (s) sda scl da(6) da(0) 7-bit device address (m) read (m) slave ack (s) d(7) d(0) 8-bit register data (s) stop (m) master no ack (m) repeat start (m) (m) => sda controlled by master (s) => sda controlled by slave
digital audio data serial interface right justified mode tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 overview (continued) similarly, in the case of an i2c register read, after the device has sent out the 8-bit data from the addressed register, if the master issues a acknowledge, the slave takes over control of sda bus and transmit for the next 8 clocks the data of the next incremental register. audio data is transferred between the host processor and the tlv320aic31 via the digital audio data serial interface, or audio bus. the audio bus of the tlv320aic31 can be configured for left or right justified, i2s, dsp, or tdm modes of operation, where communication with standard telephony pcm interfaces is supported within the tdm mode. these modes are all msb-first, with data width programmable as 16, 20, 24, or 32 bits. in addition, the word clock (wclk) and bit clock (bclk) can be independently configured in either master or slave mode, for flexible connectivity to a wide variety of processors the word clock (wclk) is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. the frequency of this clock corresponds to the maximum of the selected adc and dac sampling frequencies. the bit clock (bclk) is used to clock in and out the digital audio data across the serial bus. when in master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. in continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated, so in general the number of bit clocks per frame will be two times the data width. for example, if data width is chosen as 16-bits, then 32 bit clocks will be generated per frame. if the bit clock signal in master mode will be used by a pll in another device, it is recommended that the 16-bit or 32-bit data width selections be used. these cases result in a low jitter bit clock signal being generated, having frequencies of 32 fs or 64 fs. in the cases of 20-bit and 24-bt data width in master mode, the bit clocks generated in each frame will not all be of equal period, due to the device not having a clean 40 fs or 48 fs clock signal readily available. the average frequency of the bit clock signal is still accurate in these cases (being 40 fs or 48 fs), but the resulting clock signal has higher jitter than in the 16-bit and 32-bit cases. in 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen. the tlv320aic31 further includes programmability to tri-state the dout line during all bit clocks when valid data is not being sent. by combining this capability with the ability to program at what bit clock in a frame the audio data will begin, time-division multiplexing (tdm) can be accomplished, resulting in multiple codecs able to use a single audio serial data bus. when the audio serial data bus is powered down while configured in master mode, the pins associated with the interface will be put into a tri-state output condition. in right-justified mode, the lsb of the left channel is valid on the rising edge of the bit clock preceding the falling edge of word clock. similarly, the lsb of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock. figure 18. right justified serial bus mode operation 18 submit documentation feedback www .ti.com bclk wclk sdin/ sdout 1 0 0 1 0 1/fs lsb msb left channel right channel 2 2 n?1 n?3 n?2 n?1 n?3 n?2
left justified mode i2s mode dsp mode tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 overview (continued) in left-justified mode, the msb of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. similarly the msb of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock. figure 19. left justified serial data bus mode operation in i2s mode, the msb of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. similarly the msb of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock. figure 20. i2s serial data bus mode operation in dsp mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. each data bit is valid on the falling edge of the bit clock. 19 submit documentation feedback www .ti.com n-1 n-2 n-3 n-1 n-2 n-3 n-1 n-2 n-3 n-1 n-2 n-3
tdm data transfer tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 overview (continued) figure 21. dsp serial bus mode operation time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock bit clock mode is selected, although it is recommended to be used in either left-justified mode or dsp mode. by changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the serial data output driver (dout) can also be programmed to tri-state during all bit clocks except when valid data is being put onto the bus. this allows other codecs to be programmed with different offsets and to drive their data onto the same dout line, just in a different slot. for incoming data, the codec simply ignores data on the bus except where it is expected based on the programmed offset. note that the location of the data when an offset is programmed is different, depending on what transfer mode is selected. in dsp mode, both left and right channels of data are transferred immediately adjacent to each other in the frame. this differs from left-justified mode, where the left and right channel data will always be a half-frame apart in each frame. in this case, as the offset is programmed from zero to some higher value, both the left and right channel data move across the frame, but still stay a full half-frame apart from each other. this is depicted in figure 22 for the two cases. figure 22. dsp mode and left justified modes, showing the effect of a programmed data word offset 20 submit documentation feedback www .ti.com bclk wclk sdin/ sdout n?2 n?3 1 0 n?1 n?2 1 0 1/fs lsb msb left channel right channel n?1 msb lsb n?4 2 n?3 2 msb lsb n-1 n-2 1 0 n-1 n-2 1 0 word clock bit clock data in/out right channel data right channel data left channel data left channel data n-1 n-2 1 0 n-1 n-2 1 0 word clock bit clock data in/out dsp mode left justified mode offset offset offset
audio data converters audio clock generation tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 overview (continued) the tlv320aic31 supports the following standard audio sampling rates: 8 khz, 11.025 khz, 12 khz, 16 khz, 22.05 khz, 24 khz, 32 khz, 44.1 khz, 48 khz, 88.2 khz, and 96 khz. the converters can also operate at different sampling rates in various combinations, which are described further below. the data converters are based on the concept of an fsref rate that is used internal to the part, and it is related to the actual sampling rates of the converters through a series of ratios. for typical sampling rates, fsref will be either 44.1 khz or 48 khz, although it can realistically be set over a wider range of rates up to 53 khz, with additional restrictions applying if the pll is used. this concept is used to set the sampling rates of the adc and dac, and also to enable high quality playback of low sampling rate data, without high frequency audible noise being generated. the sampling rate of the adc and dac can be set to fsref/ndac or 2 fsref/ndac, with ndac being 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6. the audio converters in the tlv320aic31 need an internal audio master clock at a frequency of 256 fsref, which can be obtained in a variety of manners from an external clock signal applied to the device. a more detailed diagram of the audio clock section of the tlv320aic31 is shown in figure 23 . figure 23. audio clock generation processing 21 submit documentation feedback www .ti.com k*r/p 2/q pll_clkin codec codec_clkin pll_out k = j.d j = 1,2,3,..,62,63 d= 0000,0001,.,9998,9999 r= 1,2,3,4,.,15,16 p= 1,2,.,7,8 q=2,3,..,16,17 mclk bclk clkdiv_in pll_in wclk= fsref/ndac adc_fs dac_fs ndac=1,1.5,2,..,5.5,6 dac dra => ndac = 0.5 codec_clk=256*fsref clkdiv_out 1/8 plldiv_out clkdiv_clkin
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 overview (continued) the part can accept an mclk input from 512 khz to 50 mhz, which can then be passed through either a programmable divider or a pll, to get the proper internal audio master clock needed by the part. the bclk input can also be used to generate the internal audio master clock. a primary concern is proper operation of the codec at various sample rates with the limited mclk frequencies available in the system. this device includes a highly programmable pll to accommodate such situations easily. the integrated pll can generate audio clocks from a wide variety of possible mclk inputs, with particular focus paid to the standard mclk rates already widely used. when the pll is disabled, fsref = clkdiv_in / (128 q) where q = 2, 3, ? , 17 clkdiv_in can be mclk or bclk, selected by page 0, register 102, bits d7-d6. note ? when ndac = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of q are not allowed. in this mode, mclk can be as high as 50 mhz, and fsref should fall within 39 khz to 53 khz. when the pll is enabled, fsref = (pllclk_in k r) / (2048 p), where p = 1, 2, 3, ? , 8 r = 1, 2, ? , 16 k = j.d j = 1, 2, 3, ? , 63 d = 0000, 0001, 0002, 0003, ? , 9998, 9999 pllclk_in can be mclk or bclk, selected by register 102, bits d5-d4 p, r, j, and d are register programmable. j is the integer portion of k (the numbers to the left of the decimal point), while d is the fractional portion of k (the numbers to the right of the decimal point, assuming four digits of precision). examples: if k = 8.5, then j = 8, d = 5000 if k = 7.12, then j = 7, d = 1200 if k = 14.03, then j = 14, d = 0300 if k = 6.0004, then j = 6, d = 0004 when the pll is enabled and d = 0000, the following conditions must be satisfied to meet specified performance: 2 mhz ( pllclk_in / p ) 20 mhz 80 mhz (pllclk _in k r / p ) 110 mhz 4 j 55 when the pll is enabled and d 1 0000, the following conditions must be satisfied to meet specified performance: 10 mhz pllclk _in / p 20 mhz 80 mhz pllclk _in k r / p 110 mhz 4 j 11 r = 1 example: mclk = 12 mhz and fsref = 44.1 khz select p = 1, r = 1, k = 7.5264, which results in j = 7, d = 5264 example: mclk = 12 mhz and fsref = 48.0 khz select p = 1, r = 1, k = 8.192, which results in j = 8, d = 1920 22 submit documentation feedback www .ti.com
stereo audio adc tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 overview (continued) the table below lists several example cases of typical mclk rates and how to program the pll to achieve fsref = 44.1 khz or 48 khz. fsref = 44.1 khz mclk (mhz) p r j d achieved fsref % error 2.8224 1 1 32 0 44100.00 0.0000 5.6448 1 1 16 0 44100.00 0.0000 12.0 1 1 7 5264 44100.00 0.0000 13.0 1 1 6 9474 44099.71 0.0007 16.0 1 1 5 6448 44100.00 0.0000 19.2 1 1 4 7040 44100.00 0.0000 19.68 1 1 4 5893 44100.30 ?0.0007 48.0 4 1 7 5264 44100.00 0.0000 fsref = 48 khz mclk (mhz) p r j d achieved fsref % error 2.048 1 1 48 0 48000.00 0.0000 3.072 1 1 32 0 48000.00 0.0000 4.096 1 1 24 0 48000.00 0.0000 6.144 1 1 16 0 48000.00 0.0000 8.192 1 1 12 0 48000.00 0.0000 12.0 1 1 8 1920 48000.00 0.0000 13.0 1 1 7 5618 47999.71 0.0006 16.0 1 1 6 1440 48000.00 0.0000 19.2 1 1 5 1200 48000.00 0.0000 19.68 1 1 4 9951 47999.79 0.0004 48.0 4 1 8 1920 48000.00 0.0000 the tlv320aic31 includes a stereo audio adc, which uses a delta-sigma modulator with 128-times oversampling in single-rate mode, followed by a digital decimation filter. the adc supports sampling rates from 8 khz to 48 khz in single-rate mode, and up to 96 khz in dual-rate mode. whenever the adc or dac is in operation, the device requires an audio master clock be provided and appropriate audio clock generation be setup within the part. in order to provide optimal system power dissipation, the stereo adc can be powered one channel at a time, to support the case where only mono record capability is required. in addition, both channels can be fully powered or entirely powered down. the integrated digital decimation filter removes high-frequency content and downsamples the audio data from an initial sampling rate of 128 fs to the final output sampling rate of fs. the decimation filter provides a linear phase output response with a group delay of 17/fs. the ?3 db bandwidth of the decimation filter extends to 0.45 fs and scales with the sample rate (fs). the filter has minimum 75db attenuation over the stopband from 0.55 fs to 64 fs. independent digital highpass filters are also included with each adc channel, with a corner frequency that can be independently set to three different settings or can be disabled entirely. because of the oversampling nature of the audio adc and the integrated digital decimation filtering, requirements for analog anti-aliasing filtering are very relaxed. the tlv320aic31 integrates a second order analog anti-aliasing filter with 20-db attenuation at 1 mhz. this filter, combined with the digital decimation filter, provides sufficient anti-aliasing filtering without requiring additional external components. the adc is preceded by a programmable gain amplifier (pga), which allows analog gain control from 0 db to 59.5 db in steps of 0.5 db. the pga gain changes are implemented with an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-db step every one or two adc output samples, depending on the register programming (see registers page-0/reg-19 and 22). this soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. on reset, the pga gain defaults to a mute condition, and upon 23 submit documentation feedback www .ti.com
automatic gain control (agc) tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 power down, the pga soft-steps the volume to mute before shutting down. a read-only flag is set whenever the gain applied by pga equals the desired value set by the register. the soft-stepping control can also be disabled by programming a register bit. when soft stepping is enabled, the audio master clock must be applied to the part after the adc power down register is written to ensure the soft-stepping to mute has completed. when the adc powerdown flag is no longer set, the audio master clock can be shut down. an automatic gain control (agc) circuit is included with the adc and can be used to maintain nominally constant output signal amplitude when recording speech signals (it can be fully disabled if not desired). this circuitry automatically adjusts the pga gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer or farther from the microphone. the agc algorithm has several programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum pga gain applicable that allow the algorithm to be fine tuned for any particular application. the algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal. note that completely independent agc circuitry is included with each adc channel with entirely independent control over the algorithm from one channel to the next. this is attractive in cases where two microphones are used in a system, but may have different placement in the end equipment and require different dynamic performance for optimal system operation. target gain represents the nominal output level at which the agc attempts to hold the adc output signal level. the tlv320aic31 allows programming of eight different target gains, which can be programmed from ?5.5 db to ?24 db relative to a full-scale signal. since the device reacts to the signal absolute average and not to peak levels, it is recommended that the larger gain be set with enough margin to avoid clipping at the occurrence of loud sounds. attack time determines how quickly the agc circuitry reduces the pga gain when the input signal is too loud. it can be varied from 8 ms to 20 ms. decay time determines how quickly the pga gain is increased when the input signal is too low. it can be varied in the range from 100 ms to 500 ms. noise gate threshold determines the level below which if the input speech average value falls, agc considers it as a silence and hence brings down the gain to 0 db in steps of 0.5 db every fs and sets the noise threshold flag. the gain stays at 0 db unless the input speech signal average rises above the noise threshold setting. this ensures that noise does not get gained up in the absence of speech. noise threshold level in the agc algorithm is programmable from ?30 db to ?90 db relative to full scale. a disable noise gate feature is also available. this operation includes programmable debounce and hysteresis functionality to avoid the agc gain from cycling between high gain and 0 db when signals are near the noise threshold level. when the noise threshold flag is set, the status of gain applied by the agc and the saturation flag should be ignored. maximum pga gain applicable allows the user to restrict the maximum pga gain that can be applied by the agc algorithm. this can be used for limiting pga gain in situations where environmental noise is greater than programmed noise threshold. it can be programmed from 0 db to +59.5 db in steps of 0.5 db. 24 submit documentation feedback www .ti.com
stereo audio dac digital audio processing tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 figure 24. typical operation of the agc algorithm during speech recording note that the time constants here are correct when the adc is not in double-rate audio mode. the time constants are achieved using the fsref value programmed in the control registers. however, if the fsref is set in the registers to, for example, 48 khz, but the actual audio clock or pll programming actually results in a different fsref in practice, then the time constants would not be correct. the tlv320aic31 includes a stereo audio dac supporting sampling rates from 8 khz to 96 khz. each channel of the stereo audio dac consists of a digital audio processing block, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. the dac is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 khz. this is realized by keeping the upsampled rate constant at 128 fsref and changing the oversampling ratio as the input sample rate is changed. for an fsref of 48 khz, the digital delta-sigma modulator always operates at a rate of 6.144 mhz. this ensures that quantization noise generated within the delta-sigma modulator stays low within the frequency band below 20 khz at all sample rates. similarly, for an fsref rate of 44.1 khz, the digital delta-sigma modulator always operates at a rate of 5.6448 mhz. the following restrictions apply in the case when the pll is powered down and double-rate audio mode is enabled in the dac. allowed q values = 4, 8, 9, 12, 16 q values where equivalent fsref can be achieved by turning on pll q = 5, 6, 7 (set p = 5 / 6 / 7 and k = 16.0 and pll enabled) q = 10, 14 (set p = 5, 7 and k = 8.0 and pll enabled) the dac channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-d effects processing. the de-emphasis function is implemented by a programmable digital filter block with fully programmable coefficients (see page-1/reg-21-26 for left channel, page-1/reg-47-52 for right channel). if de-emphasis is not required in a particular application, this programmable filter block can be used for some other purpose. the de-emphasis filter transfer function is given by: 25 submit documentation feedback www .ti.com decay t ime input signal output signal agc gain attack time
(1) (2) tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 where the n0, n1, and d1 coefficients are fully programmable individually for each channel. the coefficients that should be loaded to implement standard de-emphasis filters are given in table 1 . table 1. de-emphasis coefficients for common audio sampling rates sampling frequency n0 n1 d1 32-khz 16950 ?1220 17037 44.1-khz 15091 ?2877 20555 48-khz (1) 14677 ?3283 21374 (1) default de-emphasis coefficients (2) in addition to the de-emphasis filter block, the dac digital effects processing includes a fourth order digital iir filter with programmable coefficients (one set per channel). this filter is implemented as cascade of two biquad sections with frequency response given by: the n and d coefficients are fully programmable, and the entire filter can be enabled or bypassed. the structure of the filtering when configured for independent channel processing is shown below in figure 25 , with lb1 corresponding to the first left-channel biquad filter using coefficients n0, n1, n2, d1, and d2. lb2 similarly corresponds to the second left-channel biquad filter using coefficients n3, n4, n5, d4, and d5. the rb1 and rb2 filters refer to the first and second right-channel biquad filters, respectively. figure 25. structure of the digital effects processing for independent channel processing the coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most commonly used in portable audio applications. the default n and d coefficients in the part are given in table 2 and implement a shelving filter with 0-db gain from dc to approximately 150 hz, at which point it rolls off to a 3-db attenuation for higher frequency signals, thus giving a 3-db boost to signals below 150 hz. the n and d coefficients are represented by 16-bit two?s complement numbers with values ranging from ?32768 to 32767. (2) 26 submit documentation feedback www .ti.com h(z) n0 n1 z 1 32768 d1 z 1 n0 2 n1 z 1 n2 z 2 32768 2 d1 z 1 d2 z 2 n3 2 n4 z 1 n5 z 2 32768 2 d4 z 1 d5 z 2 lb1 lb2 rb1 rb2
digital interpolation filter tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 table 2. default digital effects processing filter coefficients, when in independent channel processing configuration coefficients n0 = n3 d1 = d4 n1 = n4 d2 = d5 n2 = n5 27619 32131 ?27034 ?31506 26461 the digital processing also includes capability to implement 3-d processing algorithms by providing means to process the mono mix of the stereo input, and then combine this with the individual channel signals for stereo output playback. the architecture of this processing mode, and the programmable filters available for use in the system, is shown in figure 26 . note that the programmable attenuation block provides a method of adjusting the level of 3-d effect introduced into the final stereo output. this combined with the fully programmable biquad filters in the system enables the user to fully optimize the audio effects for a particular system and provide extensive differentiation from other systems using the same device. figure 26. architecture of the digital audio processing when 3-d effects are enabled it is recommended that the digital effects filters should be disabled while the filter coefficients are being modified. while new coefficients are being written to the device over the control port, it is possible that a filter using partially updated coefficients may actually implement an unstable system and lead to oscillation or objectionable audio output. by disabling the filters, changing the coefficients, and then re-enabling the filters, these types of effects can be entirely avoided. the digital interpolation filter upsamples the output of the digital audio processing block by the required oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter stages. the filter provides a linear phase output with a group delay of 21/fs. in addition, programmable digital interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the upsampling process that are below 20 khz. for example, upsampling an 8-khz signal produces signal images at multiples of 8-khz (i.e., 8 khz, 16 khz, 24 khz, etc.). the images at 8 khz and 16 khz are below 20 khz and still audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. the interpolation filter is designed to maintain at least 65-db rejection of images that land below 7.455 fs. in order to utilize the programmable interpolation capability, the fsref should be programmed to a higher rate (restricted to be in the range of 39 khz to 53 khz when the pll is in use), and the actual fs is set using the ndac divider. for example, if fs = 8 khz is required, then fsref can be set to 48 khz, and the dac fs set to fsref/6. this ensures that all images of the 8-khz data are sufficiently attenuated well beyond a 20-khz audible frequency range. 27 submit documentation feedback www .ti.com lb1 rb2 atten lb2 l r toleftchannel to right channel
delta-sigma audio dac audio dac digital volume control analog output common-mode adjustment tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 the stereo audio dac incorporates a third order multi-bit delta-sigma modulator followed by an analog reconstruction filter. the dac provides high-resolution, low-noise performance, using oversampling and noise shaping techniques. the analog reconstruction filter design consists of a 6-tap analog fir filter followed by a continuous time rc filter. the analog fir operates at a rate of 128 fsref (6.144 mhz when fsref = 48 khz, 5.6448 mhz when fsref = 44.1 khz). note that the dac analog performance may be degraded by excessive clock jitter on the mclk input. therefore, care must be taken to keep jitter on this clock to a minimum. the audio dac includes a digital volume control block which implements a programmable digital gain. the volume level can be varied from 0 db to ?63.5 db in 0.5-db steps, in addition to a mute bit, independently for each channel. the volume level of both channels can also be changed simultaneously by the master volume control. gain changes are implemented with a soft-stepping algorithm, which only changes the actual volume by one step per input sample, either up or down, until the desired volume is reached. the rate of soft-stepping can be slowed to one step per two input samples through a register bit. because of soft-stepping, the host does not know when the dac has been actually muted. this may be important if the host wishes to mute the dac before making a significant change, such as changing sample rates. in order to help with this situation, the device provides a flag back to the host via a read-only register bit that alerts the host when the part has completed the soft-stepping and the actual volume has reached the desired volume level. the soft-stepping feature can be disabled through register programming. if soft-stepping is enabled, the mclk signal should be kept applied to the device until the dac power-down flag is set. when this flag is set, the internal soft-stepping process and power down sequence is complete, and the mclk can then be stopped if desired. the tlv320aic31 also includes functionality to detect when the user switches on or off the de-emphasis or digital audio processing functions, to first (1) soft-mute the dac volume control, (2) change the operation of the digital effects processing, and (3) soft-unmute the part. this avoids any possible pop/clicks in the audio output due to instantaneous changes in the filtering. a similar algorithm is used when first powering up or down the dac. the circuit begins operation at power up with the volume control muted, then soft-steps it up to the desired volume level. at power down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry. the output common-mode voltage and output range of the analog output are determined by an internal bandgap reference, in contrast to other codecs that may use a divided version of the supply. this scheme is used to reduce the coupling of noise that may be on the supply (such as 217-hz noise in a gsm cellphone) into the audio signal path. however, due to the possible wide variation in analog supply range (2.7 v ? 3.6 v), an output common-mode voltage setting of 1.35 v, which would be used for a 2.7 v supply case, will be overly conservative if the supply is actually much larger, such as 3.3 v or 3.6 v. in order to optimize device operation, the tlv320aic31 includes a programmable output common-mode level, which can be set by register programming to a level most appropriate to the actual supply range used by a particular customer. the output common-mode level can be varied among four different values, ranging from 1.35 v (most appropriate for low supply ranges, near 2.7 v) to 1.8 v (most appropriate for high supply ranges, near 3.6 v). note that there is also some limitation on the range of dvdd voltage as well in determining which setting is most appropriate. table 3. appropriate settings cm setting recommended avdd, drvdd recommended dvdd 1.35 2.7 v ? 3.6 v 1.525 v ? 1.95 v 1.50 3.0 v ? 3.6 v 1.65 v ? 1.95 v 1.65 v 3.3 v ? 3.6 v 1.8 v ? 1.95 v 1.8 v 3.6 v 1.95 v 28 submit documentation feedback www .ti.com
audio dac power control audio analog inputs tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 the stereo dac can be fully powered up or down, and in addition, the analog circuitry in each dac channel can be powered up or down independently. this provides power savings when only a mono playback stream is needed. the tlv320aic31 includes six analog audio input pins, which can be configured as two fully-differential pair plus one single-ended pair of audio inputs, or four single-ended audio inputs. these six pins connect through series resistors and switches to the virtual ground terminals of two fully differential opamps (one per adc/pga channel). by selecting to turn on only one set of switches per opamp at a time, the inputs can be effectively muxed to each adc pga channel by selecting to turn on multiple sets of switches per opamp at a time, mixing can also be achieved. however, single-ended and fully-differential audio inputs cannot be mixed into the same adc pga at the same time. mixing of multiple inputs can easily lead to pga outputs that exceed the range of the internal opamps, resulting in saturation and clipping of the mixed output signal. whenever mixing is being implemented, the user should take adequate precautions to avoid such a saturation case from occurring. in general, the mixed signal should not exceed 2vp-p single-ended or 4vp-p fully-differential. in most mixing applications, there is also a general need to adjust the levels of the individual signals being mixed. for example, if a soft signal and a large signal are to be mixed and played together, the soft signal generally should be amplified to a level comparable to the large signal before mixing. in order to accommodate this need, the tlv320aic31 includes input level control on each of the individual inputs before they are mixed or muxed into the adc pgas, with gain programmable from 0db to -12db in 1.5db steps. note that this input level control is not intended to be a volume control, but instead used occasionally for level setting. soft-stepping of the input level control settings is implemented in this device, with the speed and functionality following the settings used by the adc pga for soft-stepping. the tlv320aic31 supports the ability to mix up to two fully-differential analog inputs into each adc pga channel. figure 27 shows the mixing configuration for the left channel, which can mix the signals in1lp-in1lm and in1rp-in1rm. figure 27. left channel fully-differential analog mixing capability two fully-differential analog inputs can similarly be mixed into the right adc pga as well, consisting of in1rp-in1rm and in1lp-in1lm. note that it is not necessary to mix both fully-differential signals if this is not desired ? unnecessary inputs can simply be muted using the input level control registers. inputs can also be selected as single-ended instead of fully-differential, and mixing or muxing into the adc pgas is also possible in this mode. it is not possible, however, for an input pair to be selected as fully-differential for connection to one adc pga and simultaneously selected as single-ended for connection to the other adc pga channel. however, it is possible for an input to be selected or mixed into both left and right channel pgas, as long as it has the same configuration for both channels (either both single-ended or both fully-differential). 29 submit documentation feedback www .ti.com gain = 0, ?1.5, ?3, . . . ?12 db, mute gain = 0, ?1.5, ?3, . . . ?12 db, mute t o left adc pga line1 lp line1 lm line1 rp line1 rm
adc pga signal bypass path functionality input impedance and vcm control tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 figure 28 shows the single-ended mixing configuration for the left channel adc pga, which enables mixing of the signals in11lp, in1rp, in2l, and in2r. the right channel adc pga mix is similar, enabling mixing of the signals in11lp, in1rp, in2l, and in2r. figure 28. left channel single-ended analog input mixing configuration in addition to the input bypass path described above, the tlv320aic31 also includes the ability to route the adc pga output signals past the adc, for mixing with other analog signals and then direction connection to the output drivers. these bypass functions are described in more detail in the sections on output mixing and output driver configurations. the tlv320aic31 includes several programmable settings to control analog input pins, particularly when they are not selected for connection to an adc pga. the default option allows unselected inputs to be put into a tri-state condition, such that the input impedance seen looking into the device is extremely high. note, however, that the pins on the device do include protection diode circuits connected to avdd and avss. thus, if any voltage is driven onto a pin approximately one diode drop (~0.6 v) above avdd or one diode drop below avss, these protection diodes will begin conducting current, resulting in an effective impedance that no longer appears as a tri-state condition. another programmable option for unselected analog inputs is to weakly hold them at the common-mode input voltage of the adc pga (which is determined by an internal bandgap voltage reference). this is useful to keep the ac-coupling capacitors connected to analog inputs biased up at a normal dc level, thus avoiding the need for them to charge up suddenly when the input is changed from being unselected to selected for connection to an adc pga. this option is controlled in page-0/reg-20 and 23. the user should ensure this option is disabled when an input is selected for connection to an adc pga or selected for the analog input bypass path, since it can corrupt the recorded input signal if left operational when an input is selected. 30 submit documentation feedback www .ti.com gain = 0, ?1.5, ?3, . . ., ?12 db, mutegain = 0, ?1.5, ?3, . . ., ?12 db, mute t o left adc pga in1 rp in2 l gain = 0, ?1.5, ?3, . . ., ?12 db, mute in1 lp in2 r gain = 0, ?1.5, ?3, . . ., ?12 db, mute
micbias generation analog fully differential line output drivers tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 in most cases, the analog input pins on the tlv320aic31 should be ac-coupled to analog input sources, the only exception to this generally being if an adc is being used for dc voltage measurement. the ac-coupling capacitor will cause a highpass filter pole to be inserted into the analog signal path, so the size of the capacitor must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed analog signal. the input impedance of the analog inputs when selected for connection to an adc pga varies with the setting of the input level control, starting at approximately 20 k w with an input level control setting of 0-db, and increasing to approximately 80-k w when the input level control is set at ?12 db. for example, using a 0.1 m f ac-coupling capacitor at an analog input will result in a highpass filter pole of 80 hz when the 0 db input level control setting is selected. the tlv320aic31 includes a programmable microphone bias output voltage (micbias), capable of providing output voltages of 2.0 v or 2.5 v (both derived from the on-chip bandgap voltage) with 4-ma output current drive. in addition, the micbias may be programmed to be switched to avdd directly through an on-chip switch, or it can be powered down completely when not needed, for power savings. this function is controlled by register programming in page-0/reg-25. the tlv320aic31 has two fully differential line output drivers, each capable of driving a 10-k w differential load. the output stage design leading to the fully differential line output drivers is shown in figure 29 and figure 30 . this design includes extensive capability to adjust signal levels independently before any mixing occurs, beyond that already provided by the pga gain and the dac digital volume control. the pga_l/r signals refer to the outputs of the adc pga stages that are similarly passed around the adc to the output stage. note that since both left and right channel signals are routed to all output drivers, a mono mix of any of the stereo signals can easily be obtained by setting the volume controls of both left and right channel signals to ?6 db and mixing them. undesired signals can also be disconnected from the mix as well through register control. figure 29. architecture of the output stage leading to the fully differential line output drivers 31 submit documentation feedback www .ti.com volume controls, mixing pga_l pga_r dac_l1dac_r1 dac_l3 left_lopleft_lom gain = 0db to +9db, mute pga_l pga_r dac_l1 dac_r1 dac_r3 right_lop right_lom gain = 0db to +9db, mute dac_l dac_l1dac_l2 dac_l3 dac_r dac_r1dac_r2 dac_r3 stereo audio dac volume controls, mixing
analog high power output drivers tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 figure 30. detail of the volume control and mixing function shown in figure 25 and figure 16 the dac_l/r signals are the outputs of the stereo audio dac, which can be steered by register control based on the requirements of the system. if mixing of the dac audio with other signals is not required, and the dac output is only needed at the stereo line outputs, then it is recommended to use the routing through path dac_l3/r3 to the fully differential stereo line outputs. this results not only in higher quality output performance, but also in lower power operation, since the analog volume controls and mixing blocks ahead of these drivers can be powered down. this connection path will attenuate the signal by a factor of 1 db. if instead the dac analog output must be routed to multiple output drivers simultaneously (such as to left_lop/m, and right_lop/m) or must be mixed with other analog signals, then the dac outputs should be switched through the dac_l1/r1 path. this option provides the maximum flexibility for routing of the dac analog signals to the output drivers the tlv320aic31 includes an output level control on each output driver with limited gain adjustment from 0 db to 9 db. the output driver circuitry in this device are designed to provide a low distortion output while playing fullscale stereo dac signals at a 0db gain setting. however, a higher amplitude output can be obtained at the cost of increased signal distortion at the output. this output level control allows the user to make this tradeoff based on the requirements of the end equipment. note that this output level control is not intended to be used as a standard output volume control. it is expected to be used only sparingly for level setting, i.e., adjustment of the fullscale output range of the device. each differential line output driver can be powered down independently of the others when it is not needed in the system. when placed into powerdown through register programming, the driver output pins will be placed into a tri-stated, high-impedance state. the tlv320aic31 includes four high power output drivers with extensive flexibility in their usage. these output drivers are individually capable of driving 40 mw each into a 16- w load in single-ended configuration, and they can be used in pairs to drive up to 500 mw into an 8- w load connected in bridge-terminated load (btl) configuration between two driver outputs. the high power output drivers can be configured in a variety of ways, including: 1. driving up to two fully differential output signals 2. driving up to four single-ended output signals 3. driving two single-ended output signals, with one or two of the remaining drivers driving a fixed vcm level, for a pseudo-differential stereo output 4. driving one or two 8- w speakers connected btl between pairs of driver output pins 5. driving stereo headphones in single-ended configuration with two drivers, while the remaining two drivers are connected in btl configuration to an 8- w speaker. the output stage architecture leading to the high power output drivers is shown in figure 31 , with the volume control and mixing blocks being effectively identical to that shown in figure 30 . note that each of these drivers have a output level control block like those included with the line output drivers, allowing gain adjustment up to +9db on the output signal. as in the previous case, this output level adjustment is not intended to be used as a standard volume control, but instead is included for additional fullscale output signal level control. 32 submit documentation feedback www .ti.com 0db to -78db 0db to -78db 0db to -78db 0db to -78db + pga_l pga_r dac_l1 dac_r1
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 two of the output drivers, hprout and hplout, include a direct connection path for the stereo dac outputs to be passed directly to the output drivers and bypass the analog volume controls and mixing networks, using the dac_l2/r2 path. as in the line output case, this functionality provides the highest quality dac playback performance with reduced power dissipation, but can only be utilized if the dac output does not need to route to multiple output drivers simultaneously, and if mixing of the dac output with other analog signals is not needed. this direct connection path will attenuate the signal by a factor of 1 db. figure 31. architecture of the output stage leading to the high power output drivers the high power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions. the user should first program the type of output configuration being used in page-0/reg-14, to allow the device to select the optimal power-up scheme to avoid output artifacts. the power-up delay time for the high power output drivers is also programmable over a wide range of time delays, from instantaneous up to 4-sec, using page-0/reg-42. when these output drivers are powered down, they can be placed into a variety of output conditions based on register programming. if lowest power operation is desired, then the outputs can be placed into a tri-state 33 submit documentation feedback www .ti.com hplouthplcom hprout hprcom dac_l2 vcm vcm pga_l dac_l1 dac_r1 volume controls, mixing pga_r dac_r2 pga_l dac_l1 dac_r1 volume controls, mixing pga_r pga_l dac_l1 dac_r1 volume controls, mixing pga_r pga_l dac_l1 dac_r1 volume controls, mixing pga_r volume level 0 db to +9 db, mute volume level 0 db to +9 db, mute volume level 0 db to +9 db, mute volume level 0 db to +9 db, mute
short circuit output protection control registers tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 condition, and all power to the output stage is removed. however, this generally results in the output nodes drifting to rest near the upper or lower analog supply, due to small leakage currents at the pins. this then results in a longer delay requirement to avoid output artifacts during driver power-on. in order to reduce this required power-on delay, the tlv320aic31 includes an option for the output pins of the drivers to be weakly driven to the vcm level they would normally rest at when powered with no signal applied. this output vcm level is determined by an internal bandgap voltage reference, and thus results in extra power dissipation when the drivers are in powerdown. however, this option provides the fastest method for transitioning the drivers from powerdown to full power operation without any output artifact introduced. the device includes a further option that falls between the other two ? while it requires less power drawn while the output drivers are in powerdown, it also takes a slightly longer delay to power-up without artifact than if the bandgap reference is kept alive. in this alternate mode, the powered-down output driver pin is weakly driven to a voltage of approximately half the drvdd supply level using an internal voltage divider. this voltage will not match the actual vcm of a fully powered driver, but due to the output voltage being close to its final value, a much shorter power-up delay time setting can be used and still avoid any audible output artifacts. these output voltage options are controlled in page-0/reg-42. the high power output drivers can also be programmed to power up first with the output level control in a highly attenuated state, then the output driver will automatically slowly reduce the output attenuation to reach the desired output level setting programmed. this capability is enabled by default but can be enabled in page-0/reg-40, d1-d0. the tlv320aic31 includes programmable short-circuit protection for the high power output drivers, for maximum flexibility in a given application. by default, if these output drivers are shorted, they will automatically limit the maximum amount of current that can be sourced to or sunk from a load, thereby protecting the device from an over-current condition. in this mode, the user can read page-0/reg-95 to determine whether the part is in short-circuit protection or not, and then decide whether to program the device to power down the output drivers. however, the device includes further capability to automatically power down an output driver whenever it does into short-circuit protection, without requiring intervention from the user. in this case, the output driver will stay in a power down condition until the user specifically programs it to power down and then power back up again, to clear the short-circuit flag. the control registers for the tlv320aic31 are described in detail below. all registers are 8 bit in width, with d7 referring to the most significant bit of each register, and d0 referring to the least significant bit. page 0 / register 0: page select register bit (1) read/ reset description write value d7?d1 x 0000000 reserved, write only zeros to these register bits d0 r/w 0 page select bit writing zero to this bit sets page-0 as the active page for following register accesses. writing a one to this bit sets page-1 as the active page for following register accesses. it is recommended that the user read this register bit back after each write, to ensure that the proper page is being accessed for future register read/writes. (1) when resetting registers related to routing and volume controls of output drivers, it is recommended to reset them by writing directly to the registers instead of using software reset. page 0 / register 1: software reset register bit read/ reset description write value d7 w 0 software reset bit 0 : don?t care 1 : self clearing software reset d6?d0 w 0000000 reserved; don?t write 34 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 2: codec sample rate select register bit read/ reset description write value d7-d4 r/w 0000 adc sample rate select 0000: adc fs = fsref/1 0001: adc fs = fsref/1.5 0010: adc fs = fsref/2 0011: adc fs = fsref/2.5 0100: adc fs = fsref/3 0101: adc fs = fsref/3.5 0110: adc fs = fsref/4 0111: adc fs = fsref/4.5 1000: adc fs = fsref/5 1001: adc fs = fsref/5.5 1010: adc fs = fsref / 6 1011?1111: reserved, do not write these sequences. note: adc sample rate must be programmed to same value as dac sample rate d3-d0 r/w 0000 dac sample rate select 0000 : dac fs = fsref/1 0001 : dac fs = fsref/1.5 0010 : dac fs = fsref/2 0011 : dac fs = fsref/2.5 0100 : dac fs = fsref/3 0101 : dac fs = fsref/3.5 0110 : dac fs = fsref/4 0111 : dac fs = fsref/4.5 1000 : dac fs = fsref/5 1001: dac fs = fsref/5.5 1010: dac fs = fsref / 6 1011?1111 : reserved, do not write these sequences. page 0 / register 3: pll programming register a bit read/ reset description write value d7 r/w 0 pll control bit 0: pll is disabled 1: pll is enabled d6?d3 r/w 0010 pll q value 0000: q = 16 0001 : q = 17 0010 : q = 2 0011 : q = 3 0100 : q = 4 ? 1110: q = 14 1111: q = 15 d2?d0 r/w 000 pll p value 000: p = 8 001: p = 1 010: p = 2 011: p = 3 100: p = 4 101: p = 5 110: p = 6 111: p = 7 35 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 4: pll programming register b bit read/ reset description write value d7?d2 r/w 000001 pll j value 000000: reserved, do not write this sequence 000001: j = 1 000010: j = 2 000011: j = 3 ? 111110: j = 62 111111: j = 63 d1?d0 r/w 00 reserved, write only zeros to these bits page 0 / register 5: pll programming register c (1) bit read/ reset description write value d7-d0 r/w 00000000 pll d value ? eight most significant bits of a 14-bit unsigned integer valid values for d are from zero to 9999, represented by a 14-bit integer located in page-0/reg-5-6. values should not be written into these registers that would result in a d value outside the valid range. (1) note that whenever the d value is changed, register 5 should be written, immediately followed by register 6. even if only the msb or lsb of the value changes, both registers should be written. page 0 / register 6: pll programming register d bit read/ reset description write value d7?d2 r/w 000000 pll d value ? six least significant bits of a 14-bit unsigned integer valid values for d are from zero to 9999, represented by a 14-bit integer located in page-0/reg-5-6. values should not be written into these registers that would result in a d value outside the valid range. d1-d0 r 00 reserved, write only zeros to these bits. page 0 / register 7: codec datapath setup register bit read/ reset description write value d7 r/w 0 fsref setting this register setting controls timers related to the agc time constants. 0: fsref = 48-khz 1: fsref = 44.1-khz d6 r/w 0 adc dual rate control 0: adc dual rate mode is disabled 1: adc dual rate mode is enabled note: adc dual rate mode must match dac dual rate mode d5 r/w 0 dac dual rate control 0: dac dual rate mode is disabled 1: dac dual rate mode is enabled d4?d3 r/w 00 left dac datapath control 00: left dac datapath is off (muted) 01: left dac datapath plays left channel input data 10: left dac datapath plays right channel input data 11: left dac datapath plays mono mix of left and right channel input data d2?d1 r/w 00 right dac datapath control 00: right dac datapath is off (muted) 01: right dac datapath plays right channel input data 10: right dac datapath plays left channel input data 11: right dac datapath plays mono mix of left and right channel input data d0 r/w 0 reserved. only write zero to this register. 36 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 8: audio serial data interface control register a bit read/ reset description write value d7 r/w 0 bit clock directional control 0: bit clock is an input (slave mode) 1: bit clock is an output (master mode) d6 r/w 0 word clock directional control 0: word clock is an input (slave mode) 1: word clock is an output (master mode) d5 r/w 0 serial output data driver (dout) 3-state control 0: do not 3-state dout when valid data is not being sent 1: 3-state dout when valid data is not being sent d4 r/w 0 bit/ word clock drive control 0: bit clock and word clock will not be transmitted when in master mode if codec is powered down 1: bit clock and word clock will continue to be transmitted when in master mode, even if codec is powered down d3 r/w 0 reserved. only write zero to this register. d2 r/w 0 3-d effect control 0: disable 3-d digital effect processing 1: enable 3-d digital effect processing d1-d0 r/w 00 reserved. only write 00 to this register page 0 / register 9: audio serial data interface control register b bit read/ reset description write value d7?d6 r/w 00 audio serial data interface transfer mode 00: serial data bus uses i2s mode 01: serial data bus uses dsp mode 10: serial data bus uses right-justified mode 11: serial data bus uses left-justified mode d5?d4 r/w 00 audio serial data word length control 00: audio data word length = 16-bits 01: audio data word length = 20-bits 10: audio data word length = 24-bits 11: audio data word length = 32-bits d3 r/w 0 bit clock rate control this register only has effect when bit clock is programmed as an output 0: continuous-transfer mode used to determine master mode bit clock rate 1: 256-clock transfer mode used, resulting in 256 bit clocks per frame d2 r/w 0 dac re-sync 0: don?t care 1: re-sync stereo dac with codec interface if the group delay changes by more than dacfs/4. d1 r/w 0 adc re-sync 0: don?t care 1: re-sync stereo adc with codec interface if the group delay changes by more than adcfs/4. d0 r/w re-sync mute behavior 0: re-sync is done without soft-muting the channel. (adc/dac) 1: re-sync is done by internally soft-muting the channel. (adc/dac) 37 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 10: audio serial data interface control register c bit read/ reset description write value d7?d0 r/w 00000000 audio serial data word offset control this register determines where valid data is placed or expected in each frame, by controlling the offset from beginning of the frame where valid data begins. the offset is measured from the rising edge of word clock when in dsp mode. note: in continuous transfer mode, the maximum offset is 17 for 12s/ljf/rjf modes and 16 for dsp mode. in 256-clock mode, the maximum offset is 241 for dsp modes. 00000000: data offset = 0 bit clocks 00000001: data offset = 1 bit clock 00000010: data offset = 2 bit clocks ? 11110001: data offset = 241 bit clocks. 11110010: data offset = 242 bit clocks 11110011-11111111: reserved. do not write these values to this register. 38 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 11: audio codec overflow flag register bit read/ reset description write value d7 r 0 left adc overflow flag this is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. the register bit reset to 0 after it is read. 0: no overflow has occurred 1: an overflow has occurred d6 r 0 right adc overflow flag this is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. the register bit reset to 0 after it is read. 0: no overflow has occurred 1: an overflow has occurred d5 r 0 left dac overflow flag this is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. the register bit reset to 0 after it is read. 0: no overflow has occurred 1: an overflow has occurred d4 r 0 right dac overflow flag this is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. the register bit reset to 0 after it is read. 0: no overflow has occurred 1: an overflow has occurred d3?d0 r/w 0001 pll r value 0000: r = 16 0001 : r = 1 0010 : r = 2 0011 : r = 3 0100 : r = 4 ? 1110: r = 14 1111: r = 15 page 0 / register 12: audio codec digital filter control register bit read/ reset description write value d7?d6 r/w 00 left adc highpass filter control 00: left adc highpass filter disabled 01: left adc highpass filter ?3-db frequency = 0.0045 adc fs 10: left adc highpass filter ?3-db frequency = 0.0125 adc fs 11: left adc highpass filter ?3-db frequency = 0.025 adc fs d5?d4 r/w 00 right adc highpass filter control 00: right adc highpass filter disabled 01: right adc highpass filter ?3-db frequency = 0.0045 adc fs 10: right adc highpass filter ?3-db frequency = 0.0125 adc fs 11: right adc highpass filter ?3-db frequency = 0.025 adc fs d3 r/w 0 left dac digital effects filter control 0: left dac digital effects filter disabled (bypassed) 1: left dac digital effects filter enabled d2 r/w 0 left dac de-emphasis filter control 0: left dac de-emphasis filter disabled (bypassed) 1: left dac de-emphasis filter enabled d1 r/w 0 right dac digital effects filter control 0: right dac digital effects filter disabled (bypassed) 1: right dac digital effects filter enabled d0 r/w 0 right dac de-emphasis filter control 0: right dac de-emphasis filter disabled (bypassed) 1: right dac de-emphasis filter enabled 39 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 13: reserved bit read/ reset description write value d7?d0 r/w 00000000 reserved. write only 00000000 to this register. page 0 / register 14: headset configuration register bit read/ reset description write value d7 r/w 0 driver capacitive coupling 0: programs high-power outputs for capless driver configuration 1: programs high-power outputs for ac-coupled driver configuration d6 (1) r/w 0 stereo output driver configuration a note: do not set bits d6 and d3 both high at the same time. 0: a stereo fully-differential output configuration is not being used 1: a stereo fully-differential output configuration is being used d5?d4 r 00 reserved. write only 00 to these bits. d3 (1) r/w 0 stereo output driver configuration b note: do not set bits d6 and d3 both high at the same time. 0: a stereo pseudo-differential output configuration is not being used 1: a stereo pseudo-differential output configuration is being used d2?d0 r 000 reserved. write only zeros to these bits. (1) do not set d6 and d3 to 1 simultaneously page 0 / register 15: left adc pga gain control register bit read/ reset description write value d7 r/w 1 left adc pga mute 0: the left adc pga is not muted 1: the left adc pga is muted d6-d0 r/w 0000000 left adc pga gain setting 0000000: gain = 0.0-db 0000001: gain = 0.5-db 0000010: gain = 1.0-db ? 1110110: gain = 59.0-db 1110111: gain = 59.5-db 1111000: gain = 59.5-db ? 1111111: gain = 59.5-db page 0 / register 16: right adc pga gain control register bit read/ reset description write value d7 r/w 1 right adc pga mute 0: the right adc pga is not muted 1: the right adc pga is muted d6-d0 r/w 0000000 right adc pga gain setting 0000000: gain = 0.0-db 0000001: gain = 0.5-db 0000010: gain = 1.0-db ? 1110110: gain = 59.0-db 1110111: gain = 59.5-db 1111000: gain = 59.5-db ? 1111111: gain = 59.5-db 40 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 17: in2l/r to left adc control register bit read/ reset description write value d7-d4 r/w 1111 in2l input level control for left adc pga mix setting the input level control to a gain below automatically connects in2l to the left adc pga mix 0000: input level control gain = 0.0-db 0001: input level control gain = ?1.5-db 0010: input level control gain = ?3.0-db 0011: input level control gain = ?4.5-db 0100: input level control gain = ?6.0-db 0101: input level control gain = ?7.5-db 0110: input level control gain = ?9.0-db 0111: input level control gain = ?10.5-db 1000: input level control gain = ?12.0-db 1001?1110: reserved. do not write these sequences to these register bits 1111: in2l is not connected to the left adc pga d3-d0 r/w 1111 in2r input level control for left adc pga mix setting the input level control to a gain below automatically connects in2r to the left adc pga mix 0000: input level control gain = 0.0-db 0001: input level control gain = ?1.5-db 0010: input level control gain = ?3.0-db 0011: input level control gain = ?4.5-db 0100: input level control gain = ?6.0-db 0101: input level control gain = ?7.5-db 0110: input level control gain = ?9.0-db 0111: input level control gain = ?10.5-db 1000: input level control gain = ?12.0-db 1001?1110: reserved. do not write these sequences to these register bits 1111: in2r is not connected to the left adc pga page 0 / register 18: in2l/r to right adc control register bit read/ reset description write value d7?d4 r/w 1111 in2l input level control for right adc pga mix setting the input level control to a gain below automatically connects in2l to the right adc pga mix 0000: input level control gain = 0.0-db 0001: input level control gain = ?1.5-db 0010: input level control gain = ?3.0-db 0011: input level control gain = ?4.5-db 0100: input level control gain = ?6.0-db 0101: input level control gain = ?7.5-db 0110: input level control gain = ?9.0-db 0111: input level control gain = ?10.5-db 1000: input level control gain = ?12.0-db 1001?1110: reserved. do not write these sequences to these register bits 1111: in2l is not connected to the right adc pga d3?d0 r/w 1111 in2r input level control for right adc pga mix setting the input level control to a gain below automatically connects in2r to the right adc pga mix 0000: input level control gain = 0.0-db 0001: input level control gain = ?1.5-db 0010: input level control gain = ?3.0-db 0011: input level control gain = ?4.5-db 0100: input level control gain = ?6.0-db 0101: input level control gain = ?7.5-db 0110: input level control gain = ?9.0-db 0111: input level control gain = ?10.5-db 1000: input level control gain = ?12.0-db 1001?1110: reserved. do not write these sequences to these register bits 1111: in2r is not connected to right adc pga 41 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 19: in1l to left adc control register bit read/ reset description write value d7 r/w 0 in1l single-ended vs fully differential control if in1l is selected to both left and right adc channels, both connections must use the same configuration (single-ended or fully differential mode). 0: in1l is configured in single-ended mode 1: in1l is configured in fully differential mode d6?d3 r/w 1111 in1l input level control for left adc pga mix setting the input level control to a gain below automatically connects in1l to the left adc pga mix 0000: input level control gain = 0.0-db 0001: input level control gain = ?1.5-db 0010: input level control gain = ?3.0-db 0011: input level control gain = ?4.5-db 0100: input level control gain = ?6.0-db 0101: input level control gain = ?7.5-db 0110: input level control gain = ?9.0-db 0111: input level control gain = ?10.5-db 1000: input level control gain = ?12.0-db 1001?1110: reserved. do not write these sequences to these register bits 1111: in1l is not connected to the left adc pga d2 r/w 0 left adc channel power control 0: left adc channel is powered down 1: left adc channel is powered up d1?d0 r/w 00 left adc pga soft-stepping control 00: left adc pga soft-stepping at once per fs 01: left adc pga soft-stepping at once per two fs 10?11: left adc pga soft-stepping is disabled page 0 / register 20: reserved register bit read/ reset description write value d7-d0 r/w 0111100 reserved. do not write to this register. 0 page 0 / register 21: in1r to left adc control register bit read/ reset description write value d7 r/w 0 in1r single-ended vs fully differential control if in1r is selected to both left and right adc channels, both connections must use the same configuration (single-ended or fully differential mode). 0: in1r is configured in single-ended mode 1: in1r is configured in fully differential mode d6?d3 r/w 1111 in1r input level control for left adc pga mix setting the input level control to a gain below automatically connects in1r to the left adc pga mix 0000: input level control gain = 0.0-db 0001: input level control gain = ?1.5-db 0010: input level control gain = ?3.0-db 0011: input level control gain = ?4.5-db 0100: input level control gain = ?6.0-db 0101: input level control gain = ?7.5-db 0110: input level control gain = ?9.0-db 0111: input level control gain = ?10.5-db 1000: input level control gain = ?12.0-db 1001?1110: reserved. do not write these sequences to these register bits 1111: in1r is not connected to the left adc pga d2?d0 r 000 reserved. write only zeros to these register bits. 42 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 22: in1r to right adc control register bit read/ reset description write value d7 r/w 0 in1r single-ended vs fully differential control if in1r is selected to both left and right adc channels, both connections must use the same configuration (single-ended or fully differential mode). 0: in1r is configured in single-ended mode 1: in1r is configured in fully differential mode d6?d3 r/w 1111 in1r input level control for right adc pga mix setting the input level control to a gain below automatically connects in1r to the right adc pga mix 0000: input level control gain = 0.0-db 0001: input level control gain = ?1.5-db 0010: input level control gain = ?3.0-db 0011: input level control gain = ?4.5-db 0100: input level control gain = ?6.0-db 0101: input level control gain = ?7.5-db 0110: input level control gain = ?9.0-db 0111: input level control gain = ?10.5-db 1000: input level control gain = ?12.0-db 1001?1110: reserved. do not write these sequences to these register bits 1111: in1r is not connected to the right adc pga d2 r/w 0 right adc channel power control 0: right adc channel is powered down 1: right adc channel is powered up d1?d0 r/w 00 right adc pga soft-stepping control 00: right adc pga soft-stepping at once per fs 01: right adc pga soft-stepping at once per two fs 10-11: right adc pga soft-stepping is disabled page 0 / register 23: reserved register bit read/ reset description write value d7-d0 r/w 0111100 reserved. do not write to this register. 0 page 0 / register 24: in1l to right adc control register bit read/ reset description write value d7 r/w 0 in1l single-ended vs fully differential control if in1l is selected to both left and right adc channels, both connections must use the same configuration (single-ended or fully differential mode). 0: in1l is configured in single-ended mode 1: in1l is configured in fully differential mode d6?d3 r/w 1111 in1l input level control for right adc pga mix setting the input level control to a gain below automatically connects in1l to the right adc pga mix 0000: input level control gain = 0.0-db 0001: input level control gain = ?1.5-db 0010: input level control gain = ?3.0-db 0011: input level control gain = ?4.5-db 0100: input level control gain = ?6.0-db 0101: input level control gain = ?7.5-db 0110: input level control gain = ?9.0-db 0111: input level control gain = ?10.5-db 1000: input level control gain = ?12.0-db 1001?1110: reserved. do not write these sequences to these register bits 1111: in1l is not connected to the right adc pga d2?d0 r 000 reserved. write only zeros to these register bits. 43 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 25: micbias control register bit read/ reset description write value d7?d6 r/w 00 micbias level control 00: micbias output is powered down 01: micbias output is powered to 2.0 v 10: micbias output is powered to 2.5 v 11: micbias output is connected to avdd d5?d3 r 000 reserved. write only zeros to these register bits. d2?d0 r xxx reserved. write only zeros to these register bits. page 0 / register 26: left agc control register a bit read/ reset description write value d7 r/w 0 left agc enable 0: left agc is disabled 1: left agc is enabled d6?d4 r/w 000 left agc target gain 000: left agc target gain = ?5.5-db 001: left agc target gain = ?8-db 010: left agc target gain = ?10-db 011: left agc target gain = ?12-db 100: left agc target gain = ?14-db 101: left agc target gain = ?17-db 110: left agc target gain = ?20-db 111: left agc target gain = ?24-db d3?d2 r/w 00 left agc attack time these time constants (1) will not be accurate when double rate audio mode is enabled. 00: left agc attack time = 8-msec 01: left agc attack time = 11-msec 10: left agc attack time = 16-msec 11: left agc attack time = 20-msec d1?d0 r/w 00 left agc decay time these time constants (1) will not be accurate when double rate audio mode is enabled. 00: left agc decay time = 100-msec 01: left agc decay time = 200-msec 10: left agc decay time = 400-msec 11: left agc decay time = 500-msec (1) time constants are valid when dra is not enabled. the values would change if dra is enabled. page 0 / register 27: left agc control register b bit read/ reset description write value d7-d1 r/w 1111111 left agc maximum gain allowed 0000000: maximum gain = 0.0-db 0000001: maximum gain = 0.5-db 0000010: maximum gain = 1.0-db ? 1110110: maximum gain = 59.0-db 1110111?111111: maximum gain = 59.5-db d0 r/w 0 reserved. write only zero to this register bit. page 0 / register 28: left agc control register c bit read/ reset description write value d7?d6 r/w 00 noise gate hysteresis level control 00: hysteresis is disabled 01: hysteresis = 1-db 10: hysteresis = 2-db 11: hysteresis = 4-db 44 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 28: left agc control register c (continued) bit read/ reset description write value d5?d1 r/w 00000 left agc noise threshold control 00000: left agc noise/silence detection disabled 00001: left agc noise threshold = ?30-db 00010: left agc noise threshold = ?32-db 00011: left agc noise threshold = ?34-db ? 11101: left agc noise threshold = ?86-db 11110: left agc noise threshold = ?88-db 11111: left agc noise threshold = ?90-db d0 r/w 0 left agc clip stepping control 0: left agc clip stepping disabled 1: left agc clip stepping enabled page 0 / register 29: right agc control register a bit read/ reset description write value d7 r/w 0 right agc enable 0: right agc is disabled 1: right agc is enabled d6-d4 r/w 000 right agc target gain 000: right agc target gain = ?5.5-db 001: right agc target gain = ?8-db 010: right agc target gain = ?10-db 011: right agc target gain = ?12-db 100: right agc target gain = ?14-db 101: right agc target gain = ?17-db 110: right agc target gain = ?20-db 111: right agc target gain = ?24-db d3?d2 r/w 00 right agc attack time these time constants will not be accurate when double rate audio mode is enabled. 00: right agc attack time = 8-msec 01: right agc attack time = 11-msec 10: right agc attack time = 16-msec 11: right agc attack time = 20-msec d1?d0 r/w 00 right agc decay time these time constants will not be accurate when double rate audio mode is enabled. 00: right agc decay time = 100-msec 01: right agc decay time = 200-msec 10: right agc decay time = 400-msec 11: right agc decay time = 500-msec page 0 / register 30: right agc control register b bit read/ reset description write value d7?d1 r/w 1111111 right agc maximum gain allowed 0000000: maximum gain = 0.0-db 0000001: maximum gain = 0.5-db 0000010: maximum gain = 1.0-db ? 1110110: maximum gain = 59.0-db 1110111?111111: maximum gain = 59.5-db d0 r/w 0 reserved. write only zero to this register bit. 45 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 31: right agc control register c bit read/ reset description write value d7?d6 r/w 00 noise gate hysteresis level control 00: hysteresis is disabled 01: hysteresis = 1-db 10: hysteresis = 2-db 11: hysteresis = 4-db d5?d1 r/w 00000 right agc noise threshold control 00000: right agc noise/silence detection disabled 00001: right agc noise threshold = ?30-db 00010: right agc noise threshold = ?32-db 00011: right agc noise threshold = ?34-db ? 11101: right agc noise threshold = ?86-db 11110: right agc noise threshold = ?88-db 11111: right agc noise threshold = ?90-db d0 r/w 0 right agc clip stepping control 0: right agc clip stepping disabled 1: right agc clip stepping enabled page 0 / register 32: left agc gain register bit read/ reset description write value d7?d0 r 00011000 left channel gain applied by agc algorithm 00000000: gain = ?12.0-db 00000001: gain = ?11.5-db 00000010: gain = ?11.0-db ? 00011000: gain = 0.0-db 00011001: gain = +0.5-db ? 10000011: gain = +59.0-db 10000100: gain = +59.5-db page 0 / register 33: right agc gain register bit read/ reset description write value d7-d0 r 00011000 right channel gain applied by agc algorithm 00000000: gain = ?12.0-db 00000001: gain = ?11.5-db 00000010: gain = ?11.0-db ? 00011000: gain = 0.0-db 00011001: gain = +0.5-db ? 10000011: gain = +59.0-db 10000100: gain = +59.5-db 46 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 34: left agc noise gate debounce register bit read/ reset description write value d7?d3 r/w 00000 left agc noise detection debounce control these times (1) will not be accurate when double rate audio mode is enabled. 00000: debounce = 0-msec 00001: debounce = 0.5-msec 00010: debounce = 1-msec 00011: debounce = 2-msec 00100: debounce = 4-msec 00101: debounce = 8-msec 00110: debounce = 16-msec 00111: debounce = 32-msec 01000: debounce = 64 1 = 64ms 01001: debounce = 64 2 = 128ms 01010: debounce = 64 3 = 192ms ? 11110: debounce = 64 23 = 1472ms 11111: debounce = 64 24 = 1536ms d2?d0 r/w 000 left agc signal detection debounce control these times (1) will not be accurate when double rate audio mode is enabled. 000: debounce = 0-msec 001: debounce = 0.5-msec 010: debounce = 1-msec 011: debounce = 2-msec 100: debounce = 4-msec 101: debounce = 8-msec 110: debounce = 16-msec 111: debounce = 32-msec (1) time constants are valid when dra is not enabled. the values would change when dra is enabled page 0 / register 35: right agc noise gate debounce register bit read/ reset description write value d7?d3 r/w 00000 right agc noise detection debounce control these times (1) will not be accurate when double rate audio mode is enabled. 00000: debounce = 0-msec 00001: debounce = 0.5-msec 00010: debounce = 1-msec 00011: debounce = 2-msec 00100: debounce = 4-msec 00101: debounce = 8-msec 00110: debounce = 16-msec 00111: debounce = 32-msec 01000: debounce = 64 1 = 64ms 01001: debounce = 64 2 = 128ms 01010: debounce = 64 3 = 192ms ? 11110: debounce = 64 23 = 1472ms 11111: debounce = 64 24 = 1536ms d2?d0 r/w 00000 right agc signal detection debounce control these times (1) will not be accurate when double rate audio mode is enabled. 000: debounce = 0-msec 001: debounce = 0.5-msec 010: debounce = 1-msec 011: debounce = 2-msec 100: debounce = 4-msec 101: debounce = 8-msec 110: debounce = 16-msec 111: debounce = 32-msec (1) time constants are valid when dra is not enabled. the values would change when dra is enabled. 47 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 36: adc flag register bit read/ reset description write value d7 r 0 left adc pga status 0: applied gain and programmed gain are not the same 1: applied gain = programmed gain d6 r 0 left adc power status 0: left adc is in a power down state 1: left adc is in a power up state d5 r 0 left agc signal detection status 0: signal power is greater than noise threshold 1: signal power is less than noise threshold d4 r 0 left agc saturation flag 0: left agc is not saturated 1: left agc gain applied = maximum allowed gain for left agc d3 r 0 right adc pga status 0: applied gain and programmed gain are not the same 1: applied gain = programmed gain d2 r 0 right adc power status 0: right adc is in a power down state 1: right adc is in a power up state d1 r 0 right agc signal detection status 0: signal power is greater than noise threshold 1: signal power is less than noise threshold d0 r 0 right agc saturation flag 0: right agc is not saturated 1: right agc gain applied = maximum allowed gain for right agc page 0 / register 37: dac power and output driver control register bit read/ reset description write value d7 r/w 0 left dac power control 0: left dac not powered up 1: left dac is powered up d6 r/w 0 right dac power control 0: right dac not powered up 1: right dac is powered up d5?d4 r/w 00 hplcom output driver configuration control 00: hplcom configured as differential of hplout 01: hplcom configured as constant vcm output 10: hplcom configured as independent single-ended output 11: reserved. do not write this sequence to these register bits. d3?d0 r 000 reserved. write only zeros to these register bits. page 0 / register 38: high power output driver control register bit read/ reset description write value d7-d6 r 00 reserved. write only zeros to these register bits. d5-d3 r/w 000 hprcom output driver configuration control 000: hprcom configured as differential of hprout 001: hprcom configured as constant vcm output 010: hprcom configured as independent single-ended output 011: hprcom configured as differential of hplcom 100: hprcom configured as external feedback with hplcom as constant vcm output 101?111: reserved. do not write these sequences to these register bits. d2 r/w 0 short circuit protection control 0: short circuit protection on all high power output drivers is disabled 1: short circuit protection on all high power output drivers is enabled d1 r/w 0 short circuit protection mode control 48 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 38: high power output driver control register (continued) bit read/ reset description write value 0: if short circuit protection enabled, it will limit the maximum current to the load 1: if short circuit protection enabled, it will power down the output driver automatically when a short is detected d0 r 0 reserved. write only zero to this register bit. page 0 / register 39: reserved register bit read/ reset description write value d7?d0 r 00000000 reserved. do not write to this register. page 0 / register 40: high power output stage control register bit read/ reset description write value d7?d6 r/w 00 output common-mode voltage control 00: output common-mode voltage = 1.35v 01: output common-mode voltage = 1.5v 10: output common-mode voltage = 1.65v 11: output common-mode voltage = 1.8v d5?d2 r/w 0000 reserved. write only 0000 to these bits. d1?d0 r/w 00 output volume control soft-stepping 00: output soft-stepping = one step per fs 01: output soft-stepping = one step per 2fs 10: output soft-stepping disabled 11: reserved. do not write this sequence to these register bits. page 0 / register 41: dac output switching control register bit read/ reset description write value d7?d6 r/w 00 left dac output switching control 00: left dac output selects dac_l1 path 01: left dac output selects dac_l3 path to left line output driver 10: left dac output selects dac_l2 path to left high power output drivers (1) 11: reserved. do not write this sequence to these register bits. d5?d4 r/w 00 right dac output switching control 00: right dac output selects dac_r1 path 01: right dac output selects dac_r3 path to right line output driver 10: right dac output selects dac_r2 path to right high power output drivers (1) 11: reserved. do not write this sequence to these register bits. d3?d2 r/w 00 reserved. write only zeros to these bits. d1?d0 r/w 00 dac digital volume control functionality 00: left and right dac channels have independent volume controls 01: left dac volume follows the right channel control register 10: right dac volume follows the left channel control register 11: left and right dac channels have independent volume controls (same as 00) (1) when using the dac direct paths (dac_l2 and dac_r2), the signal will be gained up by a factor of -1 db. 49 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 42: output driver pop reduction register bit read/ reset description write value d7-d4 r/w 0000 output driver power-on delay control 0000: driver power-on time = 0- m sec 0001: driver power-on time = 10- m sec 0010: driver power-on time = 100- m sec 0011: driver power-on time = 1-msec 0100: driver power-on time = 10-msec 0101: driver power-on time = 50-msec 0110: driver power-on time = 100-msec 0111: driver power-on time = 200-msec 1000: driver power-on time = 400-msec 1001: driver power-on time = 800-msec 1010: driver power-on time = 2-sec 1011: driver power-on time = 4-sec 1100?1111: reserved. do not write these sequences to these register bits. d3-d2 r/w 00 driver ramp-up step timing control 00: driver ramp-up step time = 0-msec 01: driver ramp-up step time = 1-msec 10: driver ramp-up step time = 2-msec 11: driver ramp-up step time = 4-msec d1 r/w 0 weak output common-mode voltage control 0: weakly driven output common-mode voltage is generated from bandgap reference 1: weakly driven output common-mode voltage is generated from resistor divider off the avdd supply d0 r/w 0 reserved. write only zero to this register bit. page 0 / register 43: left dac digital volume control register bit read/ reset description write value d7 r/w 1 left dac digital mute 0: the left dac channel is not muted 1: the left dac channel is muted d6?d0 r/w 0000000 left dac digital volume control setting 0000000: gain = 0.0-db 0000001: gain = ?0.5-db 0000010: gain = ?1.0-db ? 1111101: gain = ?62.5-db 1111110: gain = ?63.0-db 1111111: gain = ?63.5-db page 0 / register 44: right dac digital volume control register bit read/ reset description write value d7 r/w 1 right dac digital mute 0: the right dac channel is not muted 1: the right dac channel is muted d6?d0 r/w 0000000 right dac digital volume control setting 0000000: gain = 0.0-db 0000001: gain = ?0.5-db 0000010: gain = ?1.0-db ? 1111101: gain = ?62.5-db 1111110: gain = ?63.0-db 1111111: gain = ?63.5-db 50 submit documentation feedback www .ti.com
output stage volume controls tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 a basic analog volume control with range from 0 db to -78 db and mute is replicated multiple times in the output stage network, connected to each of the analog signals that route to the output stage. in addition, to enable completely independent mixing operations to be performed for each output driver, each analog signal coming into the output stage may have up to seven separate volume controls. these volume controls all have approximately 0.5-db step programmability over most of the gain range, with steps increasing slightly at the lowest attenuations. table 4 lists the detailed gain versus programmed setting for this basic volume control. table 4. output stage volume control settings and gains gain setting analog gain gain setting analog gain gain setting analog gain gain setting analog gain (db) (db) (db) (db) 0 0.0 30 -15.0 60 -30.1 90 -45.2 1 -0.5 31 -15.5 61 -30.6 91 -45.8 2 -1.0 32 -16.0 62 -31.1 92 -46.2 3 -1.5 33 -16.5 63 -31.6 93 -46.7 4 -2.0 34 -17.0 64 -32.1 94 -47.4 5 -2.5 35 -17.5 65 -32.6 95 -47.9 6 -3.0 36 -18.0 66 -33.1 96 -48.2 7 -3.5 37 -18.6 67 -33.6 97 -48.7 8 -4.0 38 -19.1 68 -34.1 98 -49.3 9 -4.5 39 -19.6 69 -34.6 99 -50.0 10 -5.0 40 -20.1 70 -35.1 100 -50.3 11 -5.5 41 -20.6 71 -35.7 101 -51.0 12 -6.0 42 -21.1 72 -36.1 102 -51.4 13 -6.5 43 -21.6 73 -36.7 103 -51.8 14 -7.0 44 -22.1 74 -37.1 104 -52.2 15 -7.5 45 -22.6 75 -37.7 105 -52.7 16 -8.0 46 -23.1 76 -38.2 106 -53.7 17 -8.5 47 -23.6 77 -38.7 107 -54.2 18 -9.0 48 -24.1 78 -39.2 108 -55.3 19 -9.5 49 -24.6 79 -39.7 109 -56.7 20 -10.0 50 -25.1 80 -40.2 110 -58.3 21 -10.5 51 -25.6 81 -40.7 111 -60.2 22 -11.0 52 -26.1 82 -41.2 112 -62.7 23 -11.5 53 -26.6 83 -41.7 113 -64.3 24 -12.0 54 -27.1 84 -42.2 114 -66.2 25 -12.5 55 -27.6 85 -42.7 115 -68.7 26 -13.0 56 -28.1 86 -43.2 116 -72.2 27 -13.5 57 -28.6 87 -43.8 117 -78.3 28 -14.0 58 -29.1 88 -44.3 118?127 mute 29 -14.5 59 -29.6 89 -44.8 page 0 / register 45: reserved register bit read/ reset description write value d7-d0 r/w 00000000 reserved. do not write to this register. 51 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 46: pga_l to hplout volume control register bit read/ reset description write value d7 r/w 0 pga_l output routing control 0: pga_l is not routed to hplout 1: pga_l is routed to hplout d6-d0 r/w 0000000 pga_l to hplout analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 47: dac_l1 to hplout volume control register bit read/ reset description write value d7 r/w 0 dac_l1 output routing control 0: dac_l1 is not routed to hplout 1: dac_l1 is routed to hplout d6-d0 r/w 0000000 dac_l1 to hplout analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 48: reserved register bit read/ reset description write value d7 r/w 00000000 reserved. do not write to this register. page 0 / register 49: pga_r to hplout volume control register bit read/ reset description write value d7 r/w 0 pga_r output routing control 0: pga_r is not routed to hplout 1: pga_r is routed to hplout d6-d0 r/w 0000000 pga_r to hplout analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 50: dac_r1 to hplout volume control register bit read/ reset description write value d7 r/w 0 dac_r1 output routing control 0: dac_r1 is not routed to hplout 1: dac_r1 is routed to hplout d6-d0 r/w 0000000 dac_r1 to hplout analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 51: hplout output level control register bit read/ reset description write value d7-d4 r/w 0000 hplout output level control 0000: output level control = 0-db 0001: output level control = 1-db 0010: output level control = 2-db ... 1000: output level control = 8-db 1001: output level control = 9-db 1010?1111: reserved. do not write these sequences to these register bits. d3 r/w 0 hplout mute 0: hplout is muted 1: hplout is not muted d2 r/w 1 hplout power down drive control 0: hplout is weakly driven to a common-mode when powered down 1: hplout is tri-stated with powered down 52 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 51: hplout output level control register (continued) bit read/ reset description write value d1 r 1 hplout volume control status 0: not all programmed gains to hplout have been applied yet 1: all programmed gains to hplout have been applied d0 r/w 0 hplout power control 0: hplout is not fully powered up 1: hplout is fully powered up page 0 / register 52: reserved register bit read/ reset description write value d7-d0 r/w 0000000 reserved. write only 00000000 to this register. page 0 / register 53: pga_l to hplcom volume control register bit read/ reset description write value d7 r/w 0 pga_l output routing control 0: pga_l is not routed to hplcom 1: pga_l is routed to hplcom d6-d0 r/w 0000000 pga_l to hplcom analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 54: dac_l1 to hplcom volume control register bit read/ reset description write value d7 r/w 0 dac_l1 output routing control 0: dac_l1 is not routed to hplcom 1: dac_l1 is routed to hplcom d6-d0 r/w 0000000 dac_l1 to hplcom analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 55: reserved register bit read/ reset description write value d7-d0 r/w 0000000 reserved. write only 0000000 to this register. page 0 / register 56: pga_r to hplcom volume control register bit read/ reset description write value d7 r/w 0 pga_r output routing control 0: pga_r is not routed to hplcom 1: pga_r is routed to hplcom d6-d0 r/w 0000000 pga_r to hplcom analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 57: dac_r1 to hplcom volume control register bit read/ reset description write value d7 r/w 0 dac_r1 output routing control 0: dac_r1 is not routed to hplcom 1: dac_r1 is routed to hplcom d6-d0 r/w 0000000 dac_r1 to hplcom analog volume control for 7-bit register setting versus analog gain values, see table 4 53 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 58: hplcom output level control register bit read/ reset description write value d7-d4 r/w 0000 hplcom output level control 0000: output level control = 0-db 0001: output level control = 1-db 0010: output level control = 2-db ... 1000: output level control = 8-db 1001: output level control = 9-db 1010?1111: reserved. do not write these sequences to these register bits. d3 r/w 0 hplcom mute 0: hplcom is muted 1: hplcom is not muted d2 r/w 1 hplcom power down drive control 0: hplcom is weakly driven to a common-mode when powered down 1: hplcom is tri-stated with powered down d1 r 1 hplcom volume control status 0: not all programmed gains to hplcom have been applied yet 1: all programmed gains to hplcom have been applied d0 r/w 0 hplcom power control 0: hplcom is not fully powered up 1: hplcom is fully powered up page 0 / register 59: reserved register bit read/ reset description write value d7-d0 r/w 0000000 reserved. write only 0000000 to this register. page 0 / register 60: pga_l to hprout volume control register bit read/ reset description write value d7 r/w 0 pga_l output routing control 0: pga_l is not routed to hprout 1: pga_l is routed to hprout d6-d0 r/w 0000000 pga_l to hprout analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 61: dac_l1 to hprout volume control register bit read/ reset description write value d7 r/w 0 dac_l1 output routing control 0: dac_l1 is not routed to hprout 1: dac_l1 is routed to hprout d6-d0 r/w 0000000 dac_l1 to hprout analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 62: reserved register bit read/ reset description write value d7-d0 r/w 0000000 reserved. write only 0000000 to this register. page 0 / register 63: pga_r to hprout volume control register bit read/ reset description write value d7 r/w 0 pga_r output routing control 0: pga_r is not routed to hprout 1: pga_r is routed to hprout 54 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 63: pga_r to hprout volume control register (continued) bit read/ reset description write value d6-d0 r/w 0000000 pga_r to hprout analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 64: dac_r1 to hprout volume control register bit read/ reset description write value d7 r/w 0 dac_r1 output routing control 0: dac_r1 is not routed to hprout 1: dac_r1 is routed to hprout d6-d0 r/w 0000000 dac_r1 to hprout analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 65: hprout output level control register bit read/ reset description write value d7-d4 r/w 0000 hprout output level control 0000: output level control = 0-db 0001: output level control = 1-db 0010: output level control = 2-db ... 1000: output level control = 8-db 1001: output level control = 9-db 1010?1111: reserved. do not write these sequences to these register bits. d3 r/w 0 hprout mute 0: hprout is muted 1: hprout is not muted d2 r/w 1 hprout power down drive control 0: hprout is weakly driven to a common-mode when powered down 1: hprout is tri-stated with powered down d1 r 1 hprout volume control status 0: not all programmed gains to hprout have been applied yet 1: all programmed gains to hprout have been applied d0 r/w 0 hprout power control 0: hprout is not fully powered up 1: hprout is fully powered up page 0 / register 66: reserved register bit read/ reset description write value d7-d0 r/w 0000000 reserved. write only 0000000 to this register. page 0 / register 67: pga_l to hprcom volume control register bit read/ reset description write value d7 r/w 0 pga_l output routing control 0: pga_l is not routed to hprcom 1: pga_l is routed to hprcom d6-d0 r/w 0000000 pga_l to hprcom analog volume control for 7-bit register setting versus analog gain values, see table 4 55 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 68: dac_l1 to hprcom volume control register bit read/ reset description write value d7 r/w 0 dac_l1 output routing control 0: dac_l1 is not routed to hprcom 1: dac_l1 is routed to hprcom d6-d0 r/w 0000000 dac_l1 to hprcom analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 69: reserved register bit read/ reset description write value d7-d0 r/w 0000000 reserved. write only 0000000 to this register. page 0 / register 70: pga_r to hprcom volume control register bit read/ reset description write value d7 r/w 0 pga_r output routing control 0: pga_r is not routed to hprcom 1: pga_r is routed to hprcom d6-d0 r/w 0000000 pga_r to hprcom analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 71: dac_r1 to hprcom volume control register bit read/ reset description write value d7 r/w 0 dac_r1 output routing control 0: dac_r1 is not routed to hprcom 1: dac_r1 is routed to hprcom d6-d0 r/w 0000000 dac_r1 to hprcom analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 72: hprcom output level control register bit read/ reset description write value d7-d4 r/w 0000 hprcom output level control 0000: output level control = 0-db 0001: output level control = 1-db 0010: output level control = 2-db ... 1000: output level control = 8-db 1001: output level control = 9-db 1010?1111: reserved. do not write these sequences to these register bits. d3 r/w 0 hprcom mute 0: hprcom is muted 1: hprcom is not muted d2 r/w 1 hprcom power down drive control 0: hprcom is weakly driven to a common-mode when powered down 1: hprcom is tri-stated with powered down d1 r 1 hprcom volume control status 0: not all programmed gains to hprcom have been applied yet 1: all programmed gains to hprcom have been applied d0 r/w 0 hprcom power control 0: hprcom is not fully powered up 1: hprcom is fully powered up 56 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 table 1. page 0 / register 73?78: reserved registers bit read/ reset description write value d7-d0 r/w 00000000 reserved. write only 00000000 to these registers. page 0 / register 79: reserved register bit read/ reset description write value d7-d0 r/w 0000010 reserved. write only 0000010 to this register. page 0 / register 80: reserved register bit read/ reset description write value d7-d0 r/w 0000000 reserved. write only 0000000 to this register. page 0 / register 81: pga_l to left_lop/m volume control register bit read/ reset description write value d7 r/w 0 pga_l output routing control 0: pga_l is not routed to left_lop/m 1: pga_l is routed to left_lop/m d6-d0 r/w 0000000 pga_l to left_lop/m analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 82: dac_l1 to left_lop/m volume control register bit read/ reset description write value d7 r/w 0 dac_l1 output routing control 0: dac_l1 is not routed to left_lop/m 1: dac_l1 is routed to left_lop/m d6-d0 r/w 0000000 dac_l1 to left_lop/m analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 83: reserved register bit read/ reset description write value d7-d0 r/w 0000000 reserved. write only 0000000 to this register. page 0 / register 84: pga_r to left_lop/m volume control register bit read/ reset description write value d7 r/w 0 pga_r output routing control 0: pga_r is not routed to left_lop/m 1: pga_r is routed to left_lop/m d6-d0 r/w 0000000 pga_r to left_lop/m analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 85: dac_r1 to left_lop/m volume control register bit read/ reset description write value d7 r/w 0 dac_r1 output routing control 0: dac_r1 is not routed to left_lop/m 1: dac_r1 is routed to left_lop/m d6-d0 r/w 0000000 dac_r1 to left_lop/m analog volume control for 7-bit register setting versus analog gain values, see table 4 57 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 86: left_lop/m output level control register bit read/ reset description write value d7-d4 r/w 0000 left_lop/m output level control 0000: output level control = 0-db 0001: output level control = 1-db 0010: output level control = 2-db ... 1000: output level control = 8-db 1001: output level control = 9-db 1010?1111: reserved. do not write these sequences to these register bits. d3 r/w 0 left_lop/m mute 0: left_lop/m is muted 1: left_lop/m is not muted d2 r/w 0 reserved. write only zero to this register bit. d1 r 1 left_lop/m volume control status 0: not all programmed gains to left_lop/m have been applied yet 1: all programmed gains to left_lop/m have been applied d0 r/w 0 left_lop/m power control 0: left_lop/m is not fully powered up 1: left_lop/m is fully powered up page 0 / register 87: reserved register bit read/ reset description write value d7-d0 r/w 0 reserved. write only 0000000 to this register. page 0 / register 88: pga_l to right_lop/m volume control register bit read/ reset description write value d7 r/w 0 pga_l output routing control 0: pga_l is not routed to right_lop/m 1: pga_l is routed to right_lop/m d6-d0 r/w 0000000 pga_l to right_lop/m analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 89: dac_l1 to right_lop/m volume control register bit read/ reset description write value d7 r/w 0 dac_l1 output routing control 0: dac_l1 is not routed to right_lop/m 1: dac_l1 is routed to right_lop/m d6-d0 r/w 0000000 dac_l1 to right_lop/m analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 90: reserved register bit read/ reset description write value d7-d0 r/w 0000000 reserved. write only 00000000 to this register. page 0 / register 91: pga_r to right_lop/m volume control register bit read/ reset description write value d7 r/w 0 pga_r output routing control 0: pga_r is not routed to right_lop/m 1: pga_r is routed to right_lop/m 58 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 91: pga_r to right_lop/m volume control register (continued) bit read/ reset description write value d6-d0 r/w 0000000 pga_r to right_lop/m analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 92: dac_r1 to right_lop/m volume control register bit read/ reset description write value d7 r/w 0 dac_r1 output routing control 0: dac_r1 is not routed to right_lop/m 1: dac_r1 is routed to right_lop/m d6-d0 r/w 0000000 dac_r1 to right_lop/m analog volume control for 7-bit register setting versus analog gain values, see table 4 page 0 / register 93: right_lop/m output level control register bit read/ reset description write value d7-d4 r/w 0000 right_lop/m output level control 0000: output level control = 0-db 0001: output level control = 1-db 0010: output level control = 2-db ... 1000: output level control = 8-db 1001: output level control = 9-db 1010?1111: reserved. do not write these sequences to these register bits. d3 r/w 0 right_lop/m mute 0: right_lop/m is muted 1: right_lop/m is not muted d2 r/w 0 reserved. write only zero to this register bit. d1 r 1 right_lop/m volume control status 0: not all programmed gains to right_lop/m have been applied yet 1: all programmed gains to right_lop/m have been applied d0 r/w 0 right_lop/m power control 0: right_lop/m is not fully powered up 1: right_lop/m is fully powered up page 0 / register 94: module power status register bit read/ reset description write value d7 r 0 left dac power status 0: left dac not fully powered up 1: left dac fully powered up d6 r 0 right dac power status 0: right dac not fully powered up 1: right dac fully powered up d5 r 0 reserved. write only zero to this bit. d4 r 0 left_lop/m power status 0: left_lop/m output driver powered down 1: left_lop/m output driver powered up d3 r 0 right_lop/m power status 0: right_lop/m is not fully powered up 1: right_lop/m is fully powered up d2 r 0 hplout driver power status 0: hplout driver is not fully powered up 1: hplout driver is fully powered up d1 r/w 0 hprout driver power status 0: hprout driver is not fully powered up 1: hprout driver is fully powered up 59 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 94: module power status register (continued) bit read/ reset description write value d0 r 0 reserved. do not write to this register bit. page 0 / register 95: output driver short circuit detection status register bit read/ reset description write value d7 r 0 hplout short circuit detection status 0: no short circuit detected at hplout 1: short circuit detected at hplout d6 r 0 hprout short circuit detection status 0: no short circuit detected at hprout 1: short circuit detected at hprout d5 r 0 hplcom short circuit detection status 0: no short circuit detected at hplcom 1: short circuit detected at hplcom d4 r 0 hprcom short circuit detection status 0: no short circuit detected at hprcom 1: short circuit detected at hprcom d3 r 0 hplcom power status 0: hplcom is not fully powered up 1: hplcom is fully powered up d2 r 0 hprcom power status 0: hprcom is not fully powered up 1: hprcom is fully powered up d1-d0 r 00 reserved. do not write to these register bits. page 0 / register 96: sticky interrupt flags register bit read/ reset description write value d7 r 0 hplout short circuit detection status 0: no short circuit detected at hplout driver 1: short circuit detected at hplout driver d6 r 0 hprout short circuit detection status 0: no short circuit detected at hprout driver 1: short circuit detected at hprout driver d5 r 0 hplcom short circuit detection status 0: no short circuit detected at hplcom driver 1: short circuit detected at hplcom driver d4 r 0 hprcom short circuit detection status 0: no short circuit detected at hprcom driver 1: short circuit detected at hprcom driver d3-d2 r 00 reserved. write only 00 to these bits. d1 r 0 left adc agc noise gate status 0: left adc signal power greater than noise threshold for left agc 1: left adc signal power lower than noise threshold for left agc d0 r 0 right adc agc noise gate status 0: right adc signal power greater than noise threshold for right agc 1: right adc signal power lower than noise threshold for right agc page 0 / register 97: real-time interrupt flags register bit read/ reset description write value d7 r 0 hplout short circuit detection status 0: no short circuit detected at hplout driver 1: short circuit detected at hplout driver 60 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 0 / register 97: real-time interrupt flags register (continued) bit read/ reset description write value d6 r 0 hprout short circuit detection status 0: no short circuit detected at hprout driver 1: short circuit detected at hprout driver d5 r 0 hplcom short circuit detection status 0: no short circuit detected at hplcom driver 1: short circuit detected at hplcom driver d4 r 0 hprcom short circuit detection status 0: no short circuit detected at hprcom driver 1: short circuit detected at hprcom driver d3-d2 r 00 reserved. write only 00 to these bits. d1 r 0 left adc agc noise gate status 0: left adc signal power greater than noise threshold for left agc 1: left adc signal power lower than noise threshold for left agc d0 r 0 right adc agc noise gate status 0: right adc signal power greater than noise threshold for right agc 1: right adc signal power lower than noise threshold for right agc page 0 / register 98?100: reserved registers bit read/ reset description write value d7-d0 r/w 00000000 reserved. write only 00000000 to these bits. page 0 / register 101: additional clock control register bit read/ reset description write value d7-d1 r/w 0000000 reserved. write only 0000000 to these bits. d0 r/w 0 codec_clkin source selection 0: codec_clkin uses plldiv_out 1: codec_clkin uses clkdiv_out page 0 / register 102: clock generation control register bit read/ reset description write value d7-d6 r/w 00 clkdiv_in source selection 00: clkdiv_in uses mclk 01: reserved. do not use. 10: clkdiv_in uses bclk 11: reserved. do not use. d5-d4 r/w 00 pllclk_in source selection 00: pllclk_in uses mclk 01: reserved. do not use. 10: pllclk _in uses bclk 11: reserved. do not use. d3-d0 r/w 0010 reserved. write only 0010 to these bits. page 0 / register 103?127: reserved registers bit read/ reset description write value d7-d0 r 00000000 reserved. do not write to these registers. page 1 / register 0: page select register bit read/ reset description write value d7-d1 x 0000000 reserved, write only zeros to these register bits 61 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 1 / register 0: page select register (continued) bit read/ reset description write value d0 r/w 0 page select bit writing zero to this bit sets page-0 as the active page for following register accesses. writing a one to this bit sets page-1 as the active page for following register accesses. it is recommended that the user read this register bit back after each write, to ensure that the proper page is being accessed for future register read/writes. this register has the same functionality on page-0 and page-1. page 1 / register 1: left channel audio effects filter n0 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x6b left channel audio effects filter n0 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 2: left channel audio effects filter n0 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0xe3 left channel audio effects filter n0 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 3: left channel audio effects filter n1 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x96 left channel audio effects filter n1 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 4: left channel audio effects filter n1 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x66 left channel audio effects filter n1 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 5: left channel audio effects filter n2 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x67 left channel audio effects filter n2 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 6: left channel audio effects filter n2 coefficient lsb bit read/ reset description write value d7-d0 r/w 0x5d left channel audio effects filter n2 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. 62 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 1 / register 7: left channel audio effects filter n3 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x6b left channel audio effects filter n3 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 8: left channel audio effects filter n3 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0xe3 left channel audio effects filter n3 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 9: left channel audio effects filter n4 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x96 left channel audio effects filter n4 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 10: left channel audio effects filter n4 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x66 left channel audio effects filter n4 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 11: left channel audio effects filter n5 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x67 left channel audio effects filter n5 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 12: left channel audio effects filter n5 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x5d left channel audio effects filter n5 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from -32768 to +32767. page 1 / register 13: left channel audio effects filter d1 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x7d left channel audio effects filter d1 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 14: left channel audio effects filter d1 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x83 left channel audio effects filter d1 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. 63 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 1 / register 15: left channel audio effects filter d2 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x84 left channel audio effects filter d2 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 16: left channel audio effects filter d2 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0xee left channel audio effects filter d2 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 17: left channel audio effects filter d4 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x7d left channel audio effects filter d4 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 18: left channel audio effects filter d4 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x83 left channel audio effects filter d4 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 19: left channel audio effects filter d5 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x84 left channel audio effects filter d5 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 20: left channel audio effects filter d5 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0xee left channel audio effects filter d5 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 21: left channel de-emphasis filter n0 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x39 left channel de-emphasis filter n0 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 22: left channel de-emphasis filter n0 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x55 left channel de-emphasis filter n0 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. 64 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 1 / register 23: left channel de-emphasis filter n1 coefficient msb register bit read/ reset description write value d7-d0 r/w 0xf3 left channel de-emphasis filter n1 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 24: left channel de-emphasis filter n1 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x2d left channel de-emphasis filter n1 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 25: left channel de-emphasis filter d1 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x53 left channel de-emphasis filter a0 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 26: left channel de-emphasis filter d1 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x7e left channel de-emphasis filter a0 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 27: right channel audio effects filter n0 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x6b right channel audio effects filter n0 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 28: right channel audio effects filter n0 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0xe3 right channel audio effects filter n0 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 29: right channel audio effects filter n1 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x96 right channel audio effects filter n1 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 30: right channel audio effects filter n1 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x66 right channel audio effects filter n1 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. 65 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 1 / register 31: right channel audio effects filter n2 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x67 right channel audio effects filter n2 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 32: right channel audio effects filter n2 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x5d right channel audio effects filter n2 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 33: right channel audio effects filter n3 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x6b right channel audio effects filter n3 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 34: right channel audio effects filter n3 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0xe3 right channel audio effects filter n3 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 35: right channel audio effects filter n4 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x96 right channel audio effects filter n4 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 36: right channel audio effects filter n4 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x66 right channel audio effects filter n4 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 37: right channel audio effects filter n5 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x67 right channel audio effects filter n5 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 38: right channel audio effects filter n5 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x5d right channel audio effects filter n5 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. 66 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 1 / register 39: right channel audio effects filter d1 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x7d right channel audio effects filter d1 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 40: right channel audio effects filter d1 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x83 right channel audio effects filter d1 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 41: right channel audio effects filter d2 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x84 right channel audio effects filter d2 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 42: right channel audio effects filter d2 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0xee right channel audio effects filter d2 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 43: right channel audio effects filter d4 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x7d right channel audio effects filter d4 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 44: right channel audio effects filter d4 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x83 right channel audio effects filter d4 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 45: right channel audio effects filter d5 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x67 right channel audio effects filter d5 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 46: right channel audio effects filter d5 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x5d right channel audio effects filter d5 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. 67 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 1 / register 47: right channel de-emphasis filter n0 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x39 right channel de-emphasis filter n0 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 48: right channel de-emphasis filter n0 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x55 right channel de-emphasis filter n0 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 49: right channel de-emphasis filter n1 coefficient msb register bit read/ reset description write value d7-d0 r/w 0xf3 right channel de-emphasis filter n1 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 50: right channel de-emphasis filter n1 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x2d right channel de-emphasis filter n1 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 51: right channel de-emphasis filter a0 coefficient msb register bit read/ reset description write value d7-d0 r/w 0x53 right channel de-emphasis filter a0 coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 52: right channel de-emphasis filter a0 coefficient lsb register bit read/ reset description write value d7-d0 r/w 0x7e right channel de-emphasis filter a0 coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 53: 3-d attenuation coefficient msb register bit read/ reset description write value d7-d0 r/w 0x7f 3-d attenuation coefficient msb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. page 1 / register 54: 3-d attenuation coefficient lsb register bit read/ reset description write value d7-d0 r/w 0xff 3-d attenuation coefficient lsb the 16-bit integer contained in the msb and lsb registers for this coefficient are interpreted as a 2?s complement integer, with possible values ranging from ?32768 to +32767. 68 submit documentation feedback www .ti.com
tlv320aic31 slas497a ? august 2006 ? revised septermber 2006 page 1 / register 55?127: reserved registers bit read/ reset description write value d7-d0 r 00000000 reserved. do not write to these registers. 69 submit documentation feedback www .ti.com
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) tlv320aic31irhbr active qfn rhb 32 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic31irhbrg4 active qfn rhb 32 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic31irhbt active qfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic31irhbtg4 active qfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 18-jul-2006 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security low power wireless www.ti.com/lpw telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2006, texas instruments incorporated

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